Bus isa purpose. ISA and EISA are among the first tire standards. Development of the module diagram

The ISA (Industrial Standard Architecture) bus is the most common in industrial computers for the following reasons:

the largest number of systems due to the low price;

a huge variety of applications;

transmission speed up to 2 Mbit/s;

good noise immunity;

a large number of compatible equipment and software.

Timing diagrams of exchange cycles for input/output devices (I/O) are shown in Figure 1.5 (all timing parameters are given for a SYSCLK frequency of 8 MHz). The cycles begin with the setting of the address by the master (bus control device) on the SAO...SA15 lines and the -SBHE signal. Note that, despite the potential ability to address 16 address lines, most often only the 10 low-order SAO...SA9 lines are used, since most previously developed expansion boards use only them, and therefore, except in special cases, there is no point in processing the high ones categories SA10...SA15.

In response to receiving the address, the performer (bus slave), which has recognized its address, must generate the -I/O CS16 signal if the exchange must be 16-bit.

Next comes the actual read or write command. During the read cycle, the master sets the -IOR signal, in response to which the executor must output data to the data bus. This data must be removed by the performer after the end of the -IOR signal. In the write cycle, the master sets the data to be written and accompanies it with the write strobe -IOW. It should be noted here that although, in accordance with the standard, setting the data to be written precedes setting -IOW, some computers implement reverse order: -IOW is set first, and then the data appears. Therefore, when designing an airwave, only the trailing (positive) edge of the -IOW signal should be considered as the moment of data validity.

In the event that the airborne device does not have time to execute the command required from it at the rate of the system bus, it can suspend the completion of the read or write cycle for an integer number of periods of the SYSCLK signal by removing (translating to a low level) the I/O CH RDY signal (the so-called extended cycle). This is done in response to receiving the -IOR or -IOW signal. The I/O CH RDY signal can be held low for no more than 15.6 µs, otherwise the processor enters non-maskable interrupt processing mode. Please note that some manufacturers personal computers indicate in the accompanying documentation other permissible values ​​of this time interval (for example, 2.5 μs), so you should not rely on the maximum value specified in the standard, otherwise there is no guarantee that the system will work in all computers.

Figure 1.5 - Timing diagrams of read and write cycles (T - period of the SYSCLK signal; all time intervals in nanoseconds)

When designing airwaves, in addition to exchange protocols over the system bus, it is also necessary to take into account the electrical characteristics of the signals. The ISA bus standard defines the input and output current requirements for the receivers and signal sources of each expansion card. Failure to comply with these requirements may disrupt the functioning of the entire computer and even cause it to fail.

The output stages of system transmitters of air-wave signals must produce current low level not less than 24 mA (this applies to all types of output stages), and the high level current is not less than 3 mA (for tri-state and TTL outputs).

System receiver input stages must consume no more than 0.8 mA of low-level input current and no more than 0.04 mA of high-level input current.

In addition, it is necessary to take into account that the maximum length of the printed conductor from the contact of the main connector to the pin of the microcircuit should not exceed 65 millimeters, and the maximum capacitance relative to ground for each contact of the main connector should not be more than 20 pF.

Load resistors are connected to some lines of the main line, going to the +5 V power bus. 4.7 kOhm resistors are connected to the lines -IOR, -IOW, -MEMR, -MEMW, -SMEMR, -SMEMW, -I/O CH SK, to lines -I/O CS 16, -MEM CS 16, -REFRESH, -MASTER, -OWS - 300 Ohm, and to the I/O CH RDY line - 1 kOhm. In addition, series resistors are connected to some lines of the trunk: 22 Ohm resistors are connected to the -IOR, -IOW, -MEMR, -MEMW, -SMEMR, -SMEMW and OSC lines, and 27 Ohm resistors are connected to the SYSCLK line.

Table 1.1 - Description of ISA bus signals

Designation	Purpose	Direction	source
	Address signals
L.A.<23...17>	Address signals
	High byte resolution on SD lines<15...8>
	Strobe for writing addresses along LA lines
	Address resolution. Informs devices that DMA loops are running on the bus
	Data bus
	Read memory (read memory within the first megabyte of address space)
	Write to memory (write to memory within the first megabyte of address space)
	Reading UVV
	Recording in UVV
	Memory cycle selection, indicates that the memory is 16-bit
	Selecting a cycle for the airwave indicates that the airwave is 16-bit
	I/O channel readiness. Designed to extend access cycles
	0 wait cycles
	Memory regeneration
	Leading. Designed to grip the tire external board
	Checking the I/O channel. Fatal error message
	Resetting devices
	System frequency
	Frequency equal to 14.3818 MHz
IRQ<15,14,12, 11,10,9,7...3>	Interrupt Request
DRQ<7...5,3...0>	Request for RAP
DASK<7...5, 3...0>	RAP confirmation
	End of DAP count

Note:

The following notations are used in the table:

the “-” (minus) sign before the signal designation means that the active level of this signal is logical zero;

I - the signal is input for external boards;

O - the signal is output for external boards;

I/O - the signal is both input and output for external boards;

THREE - output of a microcircuit with three permissible output states;

TTL - output of transistor-transistor logic chip;

OK - open collector output.

Table 1.2 - ISA bus pin assignments

Pin number	Side A	Side B	Side C	Side D

Table 1.3 - Electrical characteristics of ISA bus signal sources

transmitter	Receiver	transmitter	receiver		Transmitter

Notes:

all currents in the table are indicated in milliamps. The “-” sign in front of the current value means that the current flows from the external board into the bus slot;

a line with an open collector output can be connected to the TTL input;

along a line with an open collector output, the current Ioh (leakage current) should not exceed 0.4 milliamps for each slot.

Table 1.4 - Maximum current consumption by the external ISA bus card

Voltage

Notes:

The external board uses only the 8-bit slot;

The external board uses a 16-bit slot;

The table informs you what currents are allowed to pass through the external board connector.

ISA Bus (Industry Standard Architecture) is an expansion bus that has been used since the first PC models and has become an industry standard. The XT computer used a bus with a data width of 8 bits and addresses of 20 bits. In AT computers it was expanded to 16 data bits and 24 address bits. Structurally, as shown in Fig. 6.1, the bus is made in the form of two slot connectors with a pin pitch of 2.54 mm (0.1 inch). The ISA-8 subset uses only a 62-pin slot (rows A, B), while the ISA-16 uses an additional 36-pin slot (rows C, D). The PC/104 bus, designed for embedded PC-based controllers, differs from the usual ISA only structurally. The EISA bus, an expensive 32-bit extension of ISA, uses a “double-deck” slot that allows regular ISA cards to be installed.

A huge number of different expansion cards have been released (and continue to be released) for the ISA bus. A number of companies produce prototype cards (Prototype Card), which are printed circuit boards of full or reduced format with a mounting bracket. The boards are equipped with mandatory interface circuits - a data buffer, an address decoder and some others. The rest of the board is free, and here the developer can place a prototype version of his device. These boards are convenient for testing a new product, as well as for mounting single copies of the device when developing and manufacturing printed circuit board unprofitable.

Rice. 26 ISA slot

At any given time, the bus can be controlled by only one master device that accesses the resources (ports or memory cells) of the executor devices. The ISA bus provides the ability to access 8- or 16-bit device registers mapped to I/O and memory spaces. The range of memory addresses for devices is limited by the upper memory area UM A (АОООО-FFFFFh). For the ISA-16 bus, the CMOS Setup settings can allow space between the 15th and 16th megabytes of memory (the computer will not be able to use more than 15 MB of RAM). For the ISA bus, the upper range of I/O addresses is limited by the number of address bits used for decoding; the lower address area O-FFh is inaccessible (reserved for system board devices). The PC adopted 10-bit I/O addressing, in which address A lines were ignored by devices. Thus, the address range of ISA bus devices is limited to the area lOOh-3FFh. Subsequently, 12-bit addressing began to be used (range lOOh-FFFh). In this case, we have to take into account the possibility of the presence of old 10-bit adapters on the bus, which will “respond” to the address with the corresponding A bits in the entire valid area of ​​the 12-bit address four times (each 10-bit address will have three more 12-bit aliases ). The full 16-bit address is used only on the EISA and PCI buses.

The ISA-8 bus can provide up to 6 interrupt request lines, ISA-16 - 11. Some of them can be “taken away” by system board devices or the PCI bus.

The ISA-8 bus allows up to three 8-bit DMA channels. On the 16-bit bus, three more 16-bit and one 8-bit channels are available.

All listed bus resources must be allocated without conflict. Non-conflict presupposes the fulfillment of the conditions listed below.

• Each worker device must control the bus

data only when read from its addresses or from the DMA channel it uses. Address areas where registers are read various devices, must not intersect. Since only the current master controls the data bus when writing, the possibility of conflicts leading to data corruption is eliminated. It is not forbidden to “snoop” on write operations not addressed to this device.

• The device must assign an IRQx or DRQx line

keep it low when passive and go high to activate the request. The device has no right to control unused request lines; they must be electrically disconnected or connected to a buffer in the third state. Only one device can use one request line. Such an absurdity (from the point of view of TTL circuit design) was allowed in the first PCs and is still being replicated due to compatibility requirements.

The problem of resource allocation for old adapters was solved using jumpers, then software-configurable devices appeared, which are being replaced by automatically configured PnP boards.

The pin assignments of the ISA and EISA bus slots are shown in the table

Table 11. ISA-8, ISA-16 and EISA bus main connector

Row B	№	Row A
GND		IOCHK#
Reset		SD7
5 V		SD6
IRQ2/9"		SD5
-5 V		SD4
DRQ2		SD3
-12V		SD2
OWS#2		SD1
+12V		S.D.O.
GND		IOCHDRY
SMEMW#		AEN
SMEMR#		SA19
IOWR#		SA18
IORD#		SA17
DACK3#		SA16
DRQ3		SA15
DACK1#		SA14
DRQ1		SA13
REFRESH"		SA12
BCLK		SA11
IRO7		SA10
IRQ6		SA9
IRQ5		SA8
IRQ4		SA7
IRQ3		SA6
DACK2#		SA5
C		SA4
BALE		SA3
+5 V		SA2
Osc		SA1
GND		SA0

1 B4: XT=IRQ2, AT=IRQ9.

2 B8: XT-Card Selected.

Table 12. Additional ISA-16 and EISA bus connector

Row O	№	Row C
MEMCS16#		SBHE#
IOCS16#		LA23
IRQ10		LA22
IRQ 11		LA21
IRQ12		LA20
IRQ 15		LA19
IRQ14		LA18
DACKO#		LA17
DRQO		MEMR#
DACK5#		MEMW#
DRQ5		SD8
DACK6#		SD9
DRQ6		SD10
DACK7#		SD11
DRQ7		SD12
+5B		SD13
MASTER*		SD14
GND		SD15

ISA bus signals are natural for peripheral chips from Intel (in the style of the 8080 family). The ISA-8 signal set is extremely simple. Program access to memory cells and I/O space is provided by the following signals:

• SD - data bus. Another name for signals is Data or D.
• SA (Addr, A) - address bus.
• AEN - port addressing resolution (prohibits false

address decryption in the DMA cycle).

• IOW# (IOWC#, IOWR#) - write to the port.
• IOR# (IORC#, IORD#) - read the port.
• SMEMW* (SMEMWR#, SMWTC#) - entry to the system

memory (in the address range 0-FFFFFh).

• SMEMR* (SMEMRD#, SMRDC#) - read system

memory (in the address range 0-FFFFFh).

The signals related to interrupt request signals and DMA channels are listed below.

• IRQ2/9, IRQ - interrupt requests. Positive

a signal edge causes a hardware interrupt request. To identify the source, the high level must remain until the interrupt is acknowledged by the processor, making it difficult to separate ( sharing) interrupts. Line IRQ2/9 on XT buses causes hardware interrupt number 2, and on AT buses it causes hardware interrupt number 9.

• DRQ - requests for 8-bit DMA channels

(positive difference).

• DACK# - acknowledge requests for 8-bit channels

• TC - sign of completion of the DMA cycle counter.

The bus also has several service signals for synchronization, reset and regeneration of memory installed on the adapters.

• IOCHRDY (CHRDY, I/OCHRDY) - device readiness,

a low level lengthens the current cycle (no more than 15 x).

• BALE (ALE) - address latch enable. After him

falling edges in each processor cycle, the SA lines are guaranteed to contain a valid address.

• REFRESH* (REF#) - memory regeneration cycle (in XT

called DACKO#).

The signal appears every 15 µs, with the address bus pointing to the next memory line being regenerated.

• USNK# - channel control, low level causes NMI

CPU (resolution and indication in system ports 061h, 062h).

• RESET (RESDRV, RESETDRV) - hardware signal

reset (active level - high).

• BCLK (CLK) - bus synchronization with a frequency of about 8

MHz. PUs may not use this signal, operating only using write and read control signals.

• OSC - frequency not synchronized with the bus 14.431818

MHz (used by older display adapters).

In addition to logical signals, the bus has contacts for power distribution +5, -5, +12 and -12 V.

An additional connector that expands the bus to 16-bit contains data, address, interrupt request, and direct access lines.

• SD - data bus.
• SBHE# is a sign of the presence of data on SD lines.
• LA - non-fixed address signals requiring

latches on the fall of the BALE signal. This method of providing an address reduces the delay. In addition, the expansion board memory address decoder circuits begin decoding slightly earlier than the BALE falloff.

• IRQ, IRQ - additional requests

interrupts.

• DRQ - requests for 16-bit DMA channels

(positive difference).

• DACK# - acknowledge requests for 16-bit channels

• DRQO and DACKO* - request and confirmation of 8-bit

DMA channel freed from memory regeneration.

The following signals are associated with data bit switching.

• MEMCS16#(M16#) - the addressable device supports

16-bit memory accesses.

• IOCS16* (I/OCS16*, У16#) - addressable device

supports 16-bit port calls.

The new control signals include the following.

• MEMW# (MWTC#) - writing to memory in any area up to

• MEMR# (MRDC#) - read memory in any area up to 16

• OWS# (SRDY#, NOWS#, ENDXFR) - shortening the current

cycle initiated by the addressed device.

• MASTER* (MASTER 16#) - request from the device,

using a 16-bit DMA channel for bus control. Upon receipt of the DACK acknowledgment, the Bus-Master can seize the bus.

To transfer data from the executor to the master, read cycles of a memory cell or I/O port are used, and to transfer data from the master to the executor, write cycles of a memory cell or I/O port are used. In each cycle, the current (for the duration of this cycle) master generates the address and control signals, and in write cycles it also generates data on the bus. The addressed executing device, in accordance with the received control signals, receives (in the write cycle) or generates (in the read cycle) data. It can also, if necessary, control the cycle time and bit depth of the transmission. Generalized timing diagrams of memory read or write cycles or I/O are shown in Fig. 6.2. Here the conditional signal CMD* represents one of the following signals:

• SMEMR#, MEMR# - in the memory read cycle;
• SMEMW#, MEMW# - in the memory write cycle;
• IOR# - in the read cycle of the I/O port;
• IOW# - in the I/O port write cycle.

In each of the considered cycles, only signals from only one line can be active (low level) this list, and the AEN signal is low during the entire cycle. A DMA cycle in which this rule is not observed is discussed below, and in such a cycle the AEN signal will be high. The SMEMR* and SMEMW* signals are generated from the MEMR# and MEMW# signals, respectively, when the address is in the O-FFFFFh range. Therefore, the SMEMR* and SMEMW* signals are delayed relative to MEMR# and MEMW* by 5-10 ns.

Rice. 27. Timing diagrams of read or write cycles on the ISA bus

At the beginning of each cycle, the bus controller sets the access address: on the SA and SBHE# lines, the valid address is stored for the duration of the entire current cycle; on the 1_A lines the address is only valid at the beginning of the cycle, so it needs to be latched. Each device has an address decoder - a combinational circuit that operates only when an address related to this device is present on the bus. In the addressing phase, the devices still “do not know” which space (memory or I/O) the set address belongs to. But the address decoders are already working, and when in the next phase the control bus reports the type of operation, the addressed device is already ready to execute it. If the device uses LA lines (they are needed only for memory accesses above the FFFFFh limit), then they must pass to the address decoder through a latch register, which is “transparent” during the action of the BALE signal and fixes the state of the outputs by its fall. This allows the decoder, which always introduces some delay, to start working before the read or write control signal arrives. When accessing I/O ports, 1_A signals are not used.

If a device has more than one register (cell), then it requires several address lines to select a specific register (cell). As a rule, the most significant bits of the address bus go to the input of address decoders that generate device sampling signals, and the least significant bits go to the address inputs of the devices themselves. Then each device in space will occupy the most compact area of ​​adjacent addresses of 2P bytes in size, where n is the number of the low-order address line arriving at the decoder. Of these, 2N addresses are actually needed, where m is the number of the most senior address line involved in selecting the device register. Ideally, there should be n=m+l: with a larger value of n, the allocated (according to the decoder) address space will not be used completely and the device registers will be repeated in the allocated area 2n"m"1 times, that is, they will have alias addresses (alias ). Alias ​​addresses will differ from the true address (the minimum of all aliases) by Kx2m+1, where K is an integer. A smaller value of n is unacceptable, since then not all registers of the device will be available to the master. In principle, you can use an address decoder that works only on some part of the addresses from the 2P region (not a multiple of a power of two), if the device requires an “inconvenient” number of registers. However, in practice, “curly cutting” of areas from the address space is usually not done, so some addresses may disappear uselessly.

The data size in each access cycle is determined by the needs of the current master and the capabilities of the executor. On the IBM PC/XT, both the system bus and the ISA bus were 8-bit, so there were no bit matching issues. In the IBM PC/AT286 (and 386-SX), the system bus is already 16-bit, and in modern PCs with 32- and 64-bit system buses, the ISA bus controller is a 16-bit bus master. The motherboard has a “skew buffer”, also known as a byte shuffler, which, if necessary, translates data from the low byte of the bus to the high byte or vice versa. The control logic for this buffer uses the SBHE#, SAO, IOCS16* and MEMCS16* signals. Support for 16-bit transfers is signaled by the addressee with IOCS16* and MEMCS16* signals when its address decoder is triggered. The IOCS16# signal affects only the bit depth of calls to ports, MEMCS16* - to memory. All exchange operations (transactions) are started by the master in the same way, since he does not yet “know” the capabilities of the performer. The development of events depends on the intentions of the master and the received 16-bit transmission enable signals. On pure 16-bit machines, the start address uniquely corresponds to the byte being transferred or the low byte of the word being transferred1. On machines with 32-bit processors, the start address set on the bus at the beginning of a transaction depends on the bit width of the data planned by the master, and may depend on the position of the addressed data relative to a double-word (32-bit) boundary. 16-bit transfers are performed in 1 cycle only if transmitted to an even address (ACHO) and when the performer responds with an IOCS16* or MEMCS16* signal; otherwise, they are divided into two cycles. 32-bit transfers will be split into 2 (16+16), 3 (8+16+8) or 4 (8+8+8+8) cycles, depending on the capabilities of the performer and the parity of the address. The order in which bytes are transmitted (in time) is ambiguous (both increment and decrement of the address are possible), but in the address space they are placed in their places unambiguously.

In table 6.4 shows the states of the ISA bus signals for various options for writing to I/O ports, tested experimentally. The output of 16-bit data was performed by the OUT DX,AX command (in DX - the port address, in AX - data; AL contains the low byte, AH - the high byte), the output of 8-bit data - by the OUT DX,AL command. Somewhat unexpected (for the author) options 3 and 6 with address decrement may not occur on all motherboards, but they should be kept in mind when designing devices that claim global compatibility. True, in practice, 16-bit transfers to odd addresses are usually avoided (even purely subconsciously), and side effects from such an order are unlikely.

Table 13. Signal states for 8- and 16-bit ISA device accesses

Signal (bus)	1 cycle	2 cycle
1. Output 16-bit data to a 16-bit device at an even address
SBHE#	L
S.A.	DX(AO=0)
D	AN
D	AL
IOCS16#	L
2. Output 16-bit data to a 16-bit device at odd address xxx1,xxx5, xxx9,xxxD
SBHE#	L	H
S.A.	DX(AO=1)	DX+1 (A0=0)
D	AL
D	AL	A.H.
IOCS16#	L	L
3. Output 16-bit data to a 16-bit device at odd address xxx3, xxx7, xxxB.xxxF
SBHE#	H	L
S.A.	(A0=0)	DX (A0= 1
D		AL
D	A.H.
IOCS16*	L	L
4. Output 16-bit data to an 8-bit device at an even address
SBHE#	L	L
S.A.	DX(AO=0)	DX+1(AO=1)
D	A.H.	A.H.
D	AL	A.H.
IOCS16*	H	H
5. Output 16-bit data to an 8-bit device at odd address xxx1,xxx5, xxx9,xxxD
SBHE#	L	H
SA[1:0]	DX (A0= 1)	DX+1 (A0=0)
D	AL
D	AL	A.H.
IOCS16#	H	H
6. Output 16-bit data to an 8-bit device at odd address xxx3, xxx7, xxxB, xxxF
SBHE#	H	L
SA[1:0]	DX+1(AO=0)	DX(AO=1)
D		AL
D	A.H.	AL
IOCS16#	H	H
7. Output 8-bit data to a 16-bit device at an even address
SBHE#	H
S.A.	DX(AO=0)
D
D	AL
IOCS16*	L
8. Outputting 8-bit data to a 16-bit device at an odd address
SBHE#	L
S.A.	DX(AO=1)
D	AL
D	0(AL?)
IOCS16*	L

When valid data is placed on the SD line is determined by the read/write control signals, so the worker does not need to synchronize with the bus clock. In read cycles, the addressed slave must issue data to the bus at the beginning (fall) of the corresponding read signal (IOR#, MEMR#, SMEMR#) and hold it until the end of the signal (until the signal rises). In write cycles, the master sets the actual data slightly after the start (fall) of the write signal (IOW#, MEMW#, SMEMW#). The executing device must record this data for itself at the end of the cycle to raise the recording signal. No confirmation of cycle execution is provided from the executing device; The duration of the cycle is set by the master, but the performer may require lengthening or shortening the cycles. Using the IOCHRDY signal, the executor can extend the cycle by an arbitrary number of clock cycles, while the master will introduce additional wait states. Typically, the bus controller monitors the duration of the cycle and, when a critical time is reached, forcibly ends it (by a timeout, possibly without reporting this event). Cycles that are too long slow down the computer, and exceeding 15 μs can lead to regeneration failure and loss of data in RAM. Using the OWS# signal, the executor invites the master to shorten the cycle by eliminating the wait cycles. The response of the master to the simultaneous use of IOCHRDY and OWS# signals is unpredictable; this situation should be avoided.

The nominal cycle time is determined by the chipset and can be programmed in BIOS Setup setting the number of wait states. At the same time, memory access cycles are, as a rule, shorter than access cycles to I/O ports. Transfer width control signals are also used to control cycle time: if a device supports 16-bit transfers, it is assumed that it can operate with fewer wait clocks. This explains that in BIOS Setup, ISA cycle times are set separately for both memory and I/O, as well as for 8- and 16-bit operations. In addition to cycle time, devices can be critical to recovery time - the duration of the passive state of read-write control signals between cycles. This parameter can also be programmed in BIOS Setup and also separately for 8- and 16-bit operations.

Expansion cards for connecting to the data bus, as a rule, use buffer chips, separate for SD and SD lines. 74ALS245 (1533AP6) microcircuits are widely used here - 8-bit bidirectional transceivers. The buffer must be opened by the OE# signal (Output Enable) when an address belonging to the address range of the connected device is present on the address bus. “On duty” is the direction of transmission “from the bus to the device”; switching in the opposite direction is performed by the IOR# signal if the device represents I/O ports, or MEMRD* if the device is assigned to memory space. Thus, the buffers have the right to transfer data to the bus (control the data bus) only during the action of the read signal related to the address zone of this device. The expansion card can be a combination of 8- and 16-bit devices; for example, the once popular multicards contained a 16-bit AT A adapter and a set of 8-bit COM, LPT, GAME port controllers and a HDD controller. In such cards, the logic for managing buffers and IOCS16* and MSC16* signals is controlled by signals from the address decoder. If the device at this address is 8-bit (does not generate IOCS16* or MSC16* signals), then it has the right to allow reading only through the SD line buffer, and the high-order SD line buffer (if present on the card) must be transferred to the third state . If the device at this address is 16-bit, then it generates the IOCS16* or MSC16* signal, and the buffer resolution is controlled by the SBHE* and SAO signals. In this case, the SD line buffer is only enabled when SAO=0, and the SD line buffer is only enabled when SBHE#=L. Incorrect resolution of buffers can lead to their conflict with the motherboard byte shuffler and data corruption.

Eight-bit devices (for example, 8255, 8250, 8253, etc.) should only be connected to SD lines and should not generate IOCS16* or MSC16* signals when accessing them. No “skew” buffers (byte shufflers) are needed on interface cards.

One of the sources describes the effect of rearranging bytes when accessing an I/O port: “If you read a word from the port at an even address, the value is the same, but if at an odd address, the most significant 8 bits of the previous value become low-order, and the high-order bits of the new one = FFh.” The first suspicions fall on an error in the buffer management logic. In fact, everything is explained much more simply. Let there be a device with a two-byte register, the low byte of which has the address RO (even), the high byte has the address RO+1, and the device (and no others) does not respond to the address R+2. Let the number AA55h be written in it at the moment, then by reading the port using the IN AX, R0 command we will get AL=55h, AH=AAh in the processor registers. Now if we try to “read it at an odd address”, that is, with the command IN AX, R0+1, we get AL=AAh (the contents of RO+1, which we actually addressed!), and AH=FFh (reading result "emptiness") So this is not a “permutation effect”, but simply ignorance of the general rule of “Intel” addressing: the address of a word (double, quadruple...) is the address of its low byte. If our device uses incomplete address decryption (the SA1 line is not used either for address decryption or for register selection), then we will see a complete rearrangement of the bytes - in AH=55h, the result of reading RO at the alias address RO+2. The operating logic of the bus controller, together with all the buffers, makes access to any memory cell or port invariant to the software addressing method - what you order is what you get, but you need to take into account the peculiarities peripheral devices, which often have aliases in port addressing. Alias ​​addresses are also found in memory space (for example, copies of BIOS images under the border of the 1st and 16th megabytes of memory in “classic” PC/AT).

Tire ISA (I industrial S tandart A rhitecture) is the de facto standard bus for personal computers such as IBM PC/AT and compatibles. Tire EISA, with which a number of companies produced personal computers, lost PCI bus and is now rarely used. The main differences between the ISA bus of the IBM PC/AT personal computer and its predecessor, the IBM PC/XT bus, are as follows:

The AT bus of computers allows the use of both 16-bit I/O devices and 16-bit memory on external boards;

a 16-bit memory access cycle on an external board can be performed without inserting wait clocks;

the amount of directly addressable memory on external boards can reach 16 MB;

an external board can become a master (master) on the bus and independently access all resources both on the bus and on motherboard.

1.1. Types of devices operating on the ISA bus

When describing the bus, it is advisable to imagine a computer as consisting of a motherboard and external boards that interact with each other and the resources of the motherboard through the bus. All passive devices (that cannot become tasks) on the bus can be divided into two groups - memory and input/output devices (ports). The access cycles for each group differ from each other both in timing and in the signals generated on the bus.

Purely conditionally, for the convenience of understanding the functioning of the bus ISA, we will assume that on the computer motherboard there are the following devices that can be owners (masters) of the bus: CPU(CPU), direct memory access controller (DMA), memory regeneration controller (MRC). In addition, an external board can also be a master on the bus. When executing an access cycle on the bus, only one of the devices can be the master. Let's consider more features of these devices on the bus ISA.

Central processing unit (CPU)- is the main master on the bus. By default, the CPU will be considered the master on the bus. The DMA controller, as well as the memory regeneration controller, prohibit the operation of the CPU during their operation.

DMA controller- this device is associated with DMA mode request signals and DMA mode confirmation signals. An active DMA request signal will allow subsequent acquisition of the bus by the DMA controller to transfer data from memory to output ports or from input ports to memory.

Memory Regeneration Controller- becomes the owner of the bus and generates address and memory read signals to regenerate information in the microcircuits dynamic memory How on maternal memory, and external boards.

External board- interacts with other devices through a connector on the ISA bus. Can become a bus master for accessing memory or I/O devices.

In addition, there are a number of devices on the computer motherboard that cannot be masters on the bus, but nevertheless interact with it. These are the following devices:

Real Time Clock (Timer-Counter)- This device consists of a real-time clock to support date and time and a timer, usually based on an Intel 8254A chip. One of the timer-counters of this chip generates pulses with a period of 15 microseconds to trigger the memory regeneration controller to regenerate.

Motherboard cross- part of the motherboard that connects the bus connectors ISA to connect external boards with other resources on the motherboard.

Memory on motherboard- Some or all of the direct access memory (RAM) chips used to store CPU information. Additional memory chips can also be placed on external boards.

Interrupt controller- this device is connected to the interrupt request lines on the bus. Interrupts require further CPU maintenance.

I/O Devices- Some or all of the I/O devices (such as parallel or serial ports) can be located either on the motherboard or on external boards.

Data byte swapper- This device allows you to exchange data between 16-bit and 8-bit devices.

The architecture of the IBM PC/AT personal computer from the point of view of using the ISA bus is shown in the figure.

External cards installed in the bus connectors can be 8- and/or 16-bit. An 8-bit card has only one interface connector and can only handle 8-bit data. An 8-bit slot also cannot be a bus master. A 16-bit board must have two interface connectors - one main, the same as in 8-bit boards, and one additional. Such a board can operate with both 8- and 16-bit data and, in addition, it can be a master on the bus. The total number of boards installed in the bus connectors is limited both by the load capacity of the bus and by the design of the motherboard. Typically, you can install no more than 8 (five 16-bit and three 8-bit) external cards per bus. This limitation is also caused by the relatively small number of free DMA request lines and interrupt requests available on the bus.

2. Characteristics of masters on the bus

2.1. CPU

The central processor is the main owner of the bus by default; the DMA controller and the memory regeneration controller can become masters on the bus only by first disabling the CPU. The process of inhibiting the operation of the CPU consists of generating a request signal for the DMA and receiving a confirmation signal for the DMA.

The central processor can be the source of both 16-bit and 32-bit operations. When the CPU is a 16-bit resource, it can perform operations on both 16- and 8-bit resources on the bus. When the CPU executes a command that operates on 16-bit data, if the access resource is 8-bit, then two access cycles are performed by special hardware on the motherboard. If the CPU is 32-bit, then in hardware on the computer's motherboard, one 32-bit cycle of CPU operation with an external resource must be converted into two individual 16-bit access cycles.

Features for external boards. If the CPU is a master on the bus, then external cards can only operate in memory or I/O mode.

2.2. DMA controller

Signals to support the DMA are supplied from the connector directly to the DMA controller, which is usually made on an Intel 8237A chip. When DMA mode is requested by any device (at least one of the signals DRQ becomes active), the DMA controller seizes the bus from the CPU. Then outputting the corresponding signal -DACK means that the DMA controller has started transmitting data. DMA cycles will not execute on the bus if the signal -MASTER will be allowed from some external board.

If a DMA request is required by an I/O device, please note that DMA channels 0...3 support the transfer of only 8-bit data; all data must be transmitted only over lines SD<7...0> . Byte swapping in this case is performed in hardware on the motherboard in accordance with the signals SA0 and -SBHE. Such a swap may be required, for example, when transferring data from the high byte of 16-bit memory to an 8-bit port. DMA channels 5...7 support the transmission of 16-bit data only; all data must be transferred as 16-bit lines SD<15...0> . The memory involved in operation in the DMA mode via these channels must only be 16-bit. The byte swapper on the motherboard will not correct for data size mismatches.

NOTE: 8-bit memory, for its part, can only transfer data in DMA mode to 8-bit I/O devices; 8-bit memory cannot be used with 16-bit I/O devices.

ATTENTION! The memory regeneration controller cannot take over the bus as long as the DMA controller owns it. This means that any DMA cycle should not exceed 15 µs. Otherwise, information loss may occur in the dynamic memory chips.

FEATURES FOR EXTERNAL BOARDS

Signals for requesting and confirming the DMA mode are connected to all external boards and these signals are generated by conventional TTL outputs, so all external boards must use and analyze various DMA channels. Otherwise, there may be a conflict between external slots or with devices on the motherboard.

External slots can be either direct access memory or I/O devices when they interface with the DMA controller.

2.3. External board

External boards can operate in 5 different modes: bus master, memory and direct access I/O devices, memory and I/O devices, memory regeneration or reset. Boards can support any combination of the first four modes; All boards must obey the reset signal simultaneously.

Only 16-bit cards with two interface connectors can become masters on the bus. To capture the bus, the external board must enable the signal -DRQ and, having received a signal -DACK from the DDP controller, enable the signal -MASTER. This completes the tire capture procedure.

An external board, having captured the bus, can perform any access cycles, just like the central processor. The only limitation is the inability to perform DMA cycles, since all interface signals that control the operation of the DMA controller are connected to the motherboard and cannot be used by the DMA controller located on the external board. When the external board is a master on the bus, the DMA controller inhibits the signal AEN and this allows the I/O devices to decrypt the address normally and be accessible to the external board. When the AEN signal is prohibited, DMA transmission cycles are impossible (more details in the signal description section AEN, in Chap. 3). In addition, DMA cycles cannot be executed on the bus also because the DMA controller channel through which the bus was captured is occupied, and other channels of the DMA controller cannot be used until the previously occupied one is released, i.e. until the bus is released by the external board that has captured it.

NOTE: Software that supports the operation of an external board as a bus master must ensure that DMA channels can only be used in cascaded mode. Otherwise, the external board will not be able to capture the bus.

NOTE: The external card begins any access cycle as 16-bit, however if the signal -MEM CS16 or -I/O CS16 will not be enabled, the loop will end as 8-bit. In this case, the byte swapper on the motherboard will determine which data lines ( SD<15...8> or SD<8...0> ) a byte of information is transmitted based on signal analysis -SBHE And SA0.

ATTENTION! The external board that has captured the bus must generate a signal no less than every 15 µs -REFRESH to request the regeneration controller to regenerate memory. When performing a memory regeneration cycle, the regeneration controller generates address and command signals and analyzes the signal I/O CH RDY, but the external board that generated the signal -REFRESH, upon completion of the regeneration cycle, removes this signal and continues to remain a master on the bus. If necessary, perform several regeneration cycles signal -REFRESH can be held by an external board for the entire duration of the required number of regeneration cycles.

The memory regeneration controller cannot seize the bus itself until the DMA controller (namely, through it the external board becomes a master on the bus) releases it for the duration of regeneration by signal -REFRESH.

2.4. Direct memory or I/O access modes

An external board can operate in DMA mode only if the DMA controller is a master on the bus. In DMA mode, data is always transferred between the I/O device and the memory on the external board. In direct I/O mode, data is transferred between memory and an I/O device on an external board. An external board that responds on the bus as an 8- or 16-bit device must respectively use 8- or 16-bit DMA controller channels. In table Figure 2.2 shows the state of the signals on the bus for the DMA mode.

ATTENTION! There are some special considerations you should pay attention to when performing data transfer cycles between 8-bit I/O devices and 16-bit memory on an external board. First, the external board must analyze the signals -SBHE And SA0 to correctly identify the transmitted data.

Secondly, when writing to the airwave from memory on an external board, the byte swapper on the motherboard will determine which half of the data bus ( SD<15...8> or SD<7...0> ) the byte should be sent; After analyzing -SBHE and SA0, the external board must determine which half of the data bus to send the data byte to. Thirdly, when reading an airwave into memory on an external board, the byte swapper also sends a data byte to memory either via the higher half of the data bus SD<15...8> , or by the younger half SD<7...0> . External signal board -SBHE And SA0 must determine when to transfer its outputs to the third state on the lower half of the data bus SD<7...0> to avoid collisions on the tire.

The external board can exchange 16-bit memory in DMA mode with both 8-bit I/O devices and 16-bit ones. But, if the external board is an 8-bit memory, then in DMA mode it can only communicate with 8-bit I/O devices. Another feature applies when the DMA controller writes data to an 8-bit output device on an external board from 16-bit memory. If such an external card is installed in a 16-bit slot and can operate in 16-bit mode, it must support the high half of the data bus for this case SD<15...8> in the third state to avoid signal collision on the bus.

ATTENTION! When the DMA controller is a master on the bus, it ignores the -0WS signal, so if the external board is used as 16-bit memory and communication with it is performed by the DMA controller, the use of fast memory chips in such a board makes no sense.

Normal access to external board as memory or I/O device. An external board becomes a regular memory or I/O resource if the bus master is the CPU or another external board.

ATTENTION! There are features of this use of an external card if it is installed in a slot and participates in data exchange as an 8-bit memory or airwave during the entire access cycle. When reading data into such an external board, the byte shuffler will shuffle the data between buses SD<15...8> or SD<7...0> for proper data reception by the external board. The external board must support its outputs SD<15...8> in the third state, since otherwise a collision of signals on the data bus is inevitable.

ATTENTION! When some external boards become bus masters, they may ignore the signal I/O CH RDY or -0WS and perform the access cycle as an 8- or 16-bit memory access cycle. But any external boards must return to the master on the bus ISA These signals are optional because if the CPU is a master on the bus, it uses these signals to determine the duration of the access cycle.

2.5. Reset mode

All external cards are in reset mode when the signal is enabled RESET DRV; otherwise this mode is impossible. All tri-state outputs on the board must be in the third state and all open-collector outputs must be in the logic one state for at least 500 ns after the signal is enabled. RESET DRV. All external boards must complete their initialization within 1 ms of signal enable RESET DRV and be prepared to perform access cycles on the bus. Any operations on the bus are possible only after the signal is disabled RESET DRV.

2.6. Memory Regeneration Controller

The memory regeneration controller performs memory read cycles at special addresses on the motherboard and external boards to regenerate information in the dynamic memory chips. Every 15 µs the controller tries to acquire the bus to start the regeneration cycle. If at this moment the master on the bus is the central processor, then it frees the bus for the regeneration controller. If at this moment the bus is captured by an external board, the regeneration controller will perform a regeneration cycle only when the external board generates a signal -REFRESH. If at this moment the master on the bus was the DMA controller, then the regeneration cycle cannot be completed until it releases the bus.

When a regeneration cycle is performed, the regeneration controller generates SA address signals<7...0>with one of 256 possible regeneration addresses. Other address lines are undefined and may be in a third state. This cycle can be delayed by the I/O CH RDY signal with the signals enabled -SMEMR And -MEMR.

ATTENTION! Regeneration cycles must be performed every 15 µs to enumerate all 256 addresses in 4 ms. If this condition is not met, data stored on the heap may be lost.

3. General description of the ISA bus

This chapter discusses bus characteristics that are independent of the type of device occupying the bus.

3.1. Address space when accessing memory

Maximum memory address space supported by the bus ISA, 16 MB (24 address lines), but not all slots fully support this address space. When a bus master accesses memory on the motherboard or memory installed in a slot, it must enable signals -MEMR or -MEMW; The hardware on the motherboard additionally allows signals -SMEMR And -SMEMW, if the required address is within the first megabyte of the address space. Only lines are connected to 8-bit slots -SMEMR And -SMEMR, SD<7...0> And S.A.<19...0> ; therefore, external cards installed in 8-bit slots can either be 8-bit I/O devices only, or 8-bit memory in the first megabyte of address space. External cards installed in 8/16-bit slots accept all command signals, addresses and data; they can be either 8- or 16-bit and the memory address space on them can be anything within 16 MB. The access cycle to such external cards ends as 16-bit if the card enables the signal -I/O CS16 or -MEM CS16.

NOTE: Memory on the motherboard or external card is considered a 16-bit resource only if the signal is enabled -MEM CS16. This signal is generated from the address signals L.A.<23...17> ; therefore, 16-bit memory can only be accessed in 128 KB blocks; inside such a block, the memory cannot be partially 8-bit and partially 16-bit, since it is impossible to uniquely generate a signal by accessing a smaller block -MEM CS16. The bit depth inside such a block must be the same when accessing any address within 128 KB.

ATTENTION! Dynamic memory chips require refresh cycles every 15 µs. If refresh cycles are performed less frequently than 15 µs, the data in memory may be lost.

FEATURES FOR EXTERNAL BOARDS

Dynamic memory on the motherboard can have two types of organization - 16-bit or 32-bit. But the memory capacity on the motherboard is taken into account only by the central processor; for external boards, the dynamic memory on the motherboard is always only 16-bit. The ROM on the motherboard containing the BIOS (Base Input/Output System) is also always 16-bit.

3.2. Address space for I/O devices

The maximum address space for I/O devices supported by the ISA bus is 64 KB (16 address lines). All slots support 16 address lines. The first 256 addresses are reserved for devices located, as a rule, on the motherboard - registers of the DMA controller, interrupt controller, real-time clock, timer-counter and other devices required for AT compatibility of various computers.

FEATURES FOR EXTERNAL BOARDS

Despite the fact that all 16 address signals are available for selecting an airborne address, traditionally only the first 10 bits of the address were used for airborne addresses in the IBM PC/XT/AT series of computers. This means that the addresses from the next kilobyte blocks will be decoded in the same way as the addresses in the first kilobyte of the airwave addresses. Therefore, for newly developed external boards, one should use “windows” in the current distribution of addresses of standard airwaves for IBM PC/AT computers. To increase the number of used airwave addresses (if necessary), you can use the address space of the selected window with a shift of 1 KB or a multiple of it. Obviously, the external board in this case must decode more than 10 address lines.

3.3. Interrupt structure

Interrupt request lines are directly connected to interrupt controllers of the Intel 8259A type. The interrupt controller will respond to a request on such a line if the signal on it goes from low to high. Tire ISA does not have lines confirming receipt of an interrupt request, so the device requesting the interrupt must itself determine by the CPU reaction whether its request has been received.

FEATURES FOR EXTERNAL BOARDS

Interrupt request lines are connected to all slots and are processed by the interrupt controller on the rising edge of the signal. Before installing a new external board, if it uses an interrupt controller in its operation, you should determine whether there is a free interrupt request line and use it for the new external board. If this condition is not met, conflict situations may occur on the bus.

3.4. Byte Swapper

The CPU or external board can perform either 8-bit or 16-bit access cycles, with all cycles always starting as 16-bit and ending as 8- or 16-bit. The access cycle will be completed as 8-bit if the device being accessed inhibits the signal -I/O CS16 or -MEM CS16.

The byte swapper is always located on the motherboard. Its job is to precisely match the size of the data exchanged between devices. In Fig. Figure 3.1 shows the place of the byte swapper when transferring data between the master and the resource being accessed. In table 3.1 summarizes all the information on byte swapping during access cycles. Bytes are swapped from the bus SD<15...0> (HIGH BYTE - high byte) on SD<7...0> (LOW BYTE - low byte) or vice versa. In the table, byte transfer from the SD bus<15...0>to SD<7...0>denoted as H > L, vice versa - L< H. LL означает, что байт по младшей половине шины данных не переставляется, HH - что байт по старшей половине шины не переставляется. HH/LL - и старший и младший байт передаются каждый по своей половине шины данных и не переставляются.

Table 3.1.

Bus master			Resource being accessed		Completing the cycle
Data size			Data size		Data size	Route read write

In Fig. Figure 3.2 shows the location of the byte swapper for data transfer cycles in DMA mode. In table 3.2 summarizes all the information on byte swapping during DMA cycles. Bytes are swapped from the bus SD<15...0> (HIGH BYTE) on SD<7...0> (LOW BYTE) or vice versa. In the table, transfer a byte from the bus SD<15...0> on SD<7...0> denoted as H > L, vice versa - L< H. LL означает, что байт по младшей половине шины данных не переставляется, HH - что байт по старшей половине шины не переставляется. HH/LL - и старший и младший байт передаются каждый по своей половине шины данных и не переставляются.

Table 3.2.

I/O device	DMA controller					Completing the cycle
Data size				Data size	-MEM CS16		Data size	read write
								Forbidden

4. Description of signals on the ISA bus

This chapter describes all the signals on the ISA bus. For a better understanding of the operation of the bus, it is advisable to divide all signals into 7 groups: ADDRESSES, DATA, CLOCKING SIGNALS, COMMAND SIGNALS, DMA MODE SIGNALS, CENTRAL CONTROL SIGNALS, INTERRUPTION SIGNALS, POWER. Information about the direction of the signals (input, output or bidirectional) is given relative to the master on the bus.

4.1. Address signals

The group of address signals includes addresses generated by the current master on the bus. There are two types of address signals on the ISA bus, S.A.<19...0> And L.A.<23...17> .

S.A.<19...0>

Address signals of this type are supplied to the bus from address registers in which the address is latched. Signals S.A.<19...0> allow memory access only in the lowest megabyte of the address space. When accessing an I/O device, only signals S.A.<15...0> S.A.<19...16> undefined.

During address regeneration cycles, only signals S.A.<7...0> have a real meaning, and the state of the signals S.A.<19...8> undefined and these pins must be in the third state for all devices on the bus.

FEATURES FOR EXTERNAL BOARDS

The external board, which has become a master on the bus, must allow the signal -REFRESH to regenerate memory, in this case the external board must transfer its output address signal drivers to the third state.

L.A.<23...17>

Signals of this type enter the bus without latching into the registers. When the central processor is a master on the bus, then the values ​​of the signals on the lines L.A.<23...17> true during signal generation BALE and they can have an arbitrary value at the end of the access cycle. If the master on the bus is a DMA controller, the signals L.A.<23...17> true before the signal starts -MEMR or -MEMW and are stored until the end of the cycle. When performing memory access cycles, signals L.A.<23...17> are always true, and when accessing I/O devices, these signals are at a logical level of "0".

When performing regeneration cycles, the state of the lines L.A.<23...17> is undefined and all resources on the bus must maintain their outputs on these lines in the third state.

RECOMMENDATIONS: For “latching” signals L.A. Only registers with potential input should be used. This is because in this case the new true address will appear at the register output at the start of the signal BALE(and not on its falling edge) and, in addition, during memory access cycles by some other master, and not the CPU, the signal BALE is maintained in the logical "1" state and the register with the potential input will simply become a signal repeater L.A.(which is what is required in this case).

FEATURES FOR EXTERNAL BOARDS

If the external board is a master on the bus, then the signals L.A.<23...17> must be true before the signal starts -MEMR or -MEMW and remain so until the end of the cycle. -REFRESH(it should be remembered that the external board can only do this by being a master on the bus), then the regeneration controller will generate address signals, so the external board should transfer its address outputs to the third state.

Signal -SBHE(System Bus High Enable - Enable the high byte on the system bus) is enabled by the central processor to indicate to all resources on the bus that the lines SD<15...8> a byte of data is sent. Signals -SBHE And SA0 are used to determine which byte is sent on which half of the data bus (in accordance with Table 3.1).

Signal -SBHE is not generated by the regeneration controller when it seizes the bus, since there are no byte rearrangements real reading data.

FEATURES FOR EXTERNAL BOARDS

If an external board becomes a master on the bus, then it must produce a signal -SBHE just like the central processor.

If an external board, which is a master on the bus, generates a signal -REFRESH, then its signal output -SBHE must be transferred to the third state.

BALE

Signal BALE(Bus Address Latch Enable - Permission to “latch” an address on the bus) is a strobe for writing addresses along lines L.A.<23...17> and tells resources on the bus that the address is true and can be latched into the register. This signal also informs resources on the bus that the signals S.A.<19...0> And -SBHE are true.

When the bus is captured by the DMA controller, the signal BALE is always equal to logical "1" (produced on the motherboard), since the signals L.A.<23...17> And S.A.<19...0> true before command signals are generated. If the regeneration controller becomes a master on the bus, then on the line BALE logic one level is also supported since address signals S.A.<19...0> true before the start of command signals.

FEATURES FOR EXTERNAL BOARDS

When the bus is captured by an external board, the signal BALE supported motherboard in a logical "1" state for the entire time of bus capture. Address signals L.A.<23...17> And S.A.<19...0> must be true during the time the board enables command signals.

If the central processor is a master on the bus and performs a resource access cycle on an external board, then the signals L.A.<23...17> are true only for a short time, so the BALE signal must be used to "latch" the address into the register. When the bus is captured by any device other than the CPU, the BALE line is maintained at a logical level of "1".

AEN

Signal AEN Address Enable is enabled when the DMA controller becomes a master on the bus and informs all resources on the bus that DMA cycles are running on the bus. Allowed signal AEN also informs all I/O devices that the DMA controller has set the memory address and the I/O device should be disabled for the duration of the signal AEN address decoding.

This signal is disabled if the master on the bus is a central processor or a regeneration controller.

FEATURES FOR EXTERNAL BOARDS

If an external board generates the -MASTER signal while performing the bus acquisition procedure, the AEN signal is disabled by the DMA controller in order to allow the external board access to I/O devices.

SD<7...0> And SD<15...8>

Lines SD<7...0> And SD<15...8> , as a rule, is also called a data bus, and along the line SD15 the most significant bit is transmitted, and along the line SD0- least significant bit. SD lines<7...0>- low half of the data bus, SD<15...0> - the high half of the data bus. All 8-bit resources can communicate only on the low half of the data bus. Data exchange between a 16-bit master on the bus and an 8-bit resource is supported by a byte swapper on the motherboard (Table 3.1 and Fig. 3.1 illustrate its operation).

FEATURES FOR EXTERNAL BOARDS

If the signal - REFRESH enabled, then external boards must transfer their outputs on the data bus to the third state, since there are no data transfers during memory regeneration cycles.

4.2. Command signals

Signals in this group control both the duration and types of access cycles performed on the bus. The group consists of six command signals, two ready signals and three signals that determine the size and type of the cycle.

Command signals determine the type of device (memory or airwave) and the direction of transfer (writing or reading).

Ready signals control the duration of the access cycle, shortening it or, conversely, lengthening it.

-MEMR And -SMEMR

Signal -MEMR(Memory Read) is enabled by the master on the bus to read data from memory at the address determined by the signals along the lines L.A.<23...17> And S.A.<19...0> . Signal -SMEMR(System Memory Read) is functionally identical to -MEMR, except that the signal -SMEMR enabled when reading memory within the first megabyte of the address space. Signal -SMEMR -MEMR -MEMR by 10 nanoseconds or less.

FEATURES FOR EXTERNAL BOARDS

-MEMR, since the signal -SMEMR can only be resolved by the motherboard when reading from memory in the first megabyte of the address space. If the external board allows the signal -REFRESH -MEMR to the third state, so after the signal is resolved -REFRESH the regeneration controller will enable this signal.

-MEMW And -SMEMW

Signal -MEMW(Memory Write) is enabled by the master on the bus to write data to memory at the address determined by the signals along the lines L.A.<23...17> And S.A.<19...0> . Signal -SMEMW(System Memory Write) is functionally identical to -MEMW, except that the signal -SMEMW enabled when writing to memory within the first megabyte of address space. Signal -SMEMW generated on the motherboard from the signal -MEMW and is therefore delayed relative to the signal -MEMR by 10 ns or less.

FEATURES FOR EXTERNAL BOARDS

If an external board becomes a master on the bus, it can only enable the signal -MEMW, since the signal -SMEMW can only be resolved by the motherboard when writing to memory in the first megabyte of the address space. If the external board allows the signal -REFRESH, then it must switch its output according to the signal -MEMW to the third state.

-I/OR

Signal -I/OR(I/O Read - Reading an input/output device) is enabled by a master on the bus to read data from an input/output device at an address determined by signals S.A.<15...0> .

FEATURES FOR EXTERNAL BOARDS

If the external board allows the signal -REFRESH, then it must switch its output according to the signal -I/OR to the third state.

-I/OW

Signal -I/OW(I/O Write - Writing to I/O devices) is enabled by a master on the bus to write data to an I/O device at an address determined by signals S.A.<15...0> .

FEATURES FOR EXTERNAL BOARDS

If the external board allows the signal -REFRESH, then it must switch its output according to the signal -IOW to the third state.

-MEM CS16

Signal -MEM CS16 Memory Cycle Select is enabled by 16-bit memory to tell the bus master that the memory it is accessing is 16-bit and should perform a 16-bit access cycle. If this signal is disabled, then only an 8-bit access cycle can be performed on the bus. The memory being accessed must generate this signal from the address signals L.A.<23...17> .

-MEM CS16

RECOMMENDATIONS: Decoding signals L.A. on an external 16-bit memory board, the signal should be enabled -MEM CS16, if the address set on the bus is the address of this external board. Since this signal is fixed on the motherboard, as a rule, at the falling edge of the signal BALE, then the circuit for decoding LA signals and subsequent formation -MEM CS16 must have the minimum possible latency (for computers with a CPU clock speed of 20 MHz, no more than 20 ns).

FEATURES FOR EXTERNAL BOARDS

If the external board is a 16-bit memory, then it must inform the master on the bus about this by enabling the signal -MEM CS16.

S.A.<15...0> and some I/O device will randomly enable the signal when decoding this address -I/O CS16, then the external board should ignore it during the memory access cycle.

-I/O CS16

Signal -I/O CS16(I/O Cycle Select) is enabled by the 16-bit I/O to inform the bus master that the I/O it is accessing has a 16-bit organization and it should perform a 16-bit access cycle. If this signal is disabled, then only an 8-bit airborne access cycle can be performed on the bus. The airborne device to which the access cycle is performed must generate this signal from the address signals S.A.<15...0> .

NOTE: The DMA controller and the regeneration controller ignore the signal -I/O CS16 when performing DAP and memory regeneration cycles.

FEATURES FOR EXTERNAL BOARDS

If the external board is a 16-bit airborne device, then it must inform the master on the bus about this by enabling the signal -I/O CS16.

If the external board, being a master controller on the bus, generates address signals L.A.<23...17> and some memory device will randomly enable the signal when decoding this address -MEM CS16, then the external board must ignore it during the access cycle to the airborne device.

I/O CH RDY

Signal I/O CH RDY(I/O Channel Ready) is an asynchronous signal generated by the device being accessed on the bus. If this signal is disabled, the access cycle will be lengthened, since wait cycles will be added to it for the duration of the prohibition. When the master on the bus is a central processor or an external board, then each waiting cycle is half the frequency period SYSCLK(for clock frequency SYSCLK=8 MHz wait clock duration - 62.5 ns). If the master on the bus is a DDP controller, then each wait cycle is one period SYSCLK(For SYSCLK=8 MHz - 125 ns). When accessing memory on an external board, the CPU always automatically inserts one wait cycle (if the signal -0WS disabled), therefore, if the external board has enough cycle time with one wait cycle, then disable the signal I/O CH RDY not required.

NOTE: When executing DMA cycles, I/O devices should not generate this signal, since the I/O device only enables the DRQ signal after true data can be received or sent by the I/O device and additional cycle time control is required by the signal. I/O CH RDY No. Only memory devices during DMA cycles can enable this signal.

WARNING: Signal I/O CH RDY cannot be disabled for a time greater than 15 μs, since if this requirement is violated, data loss in the dynamic memory chips is possible.

FEATURES FOR EXTERNAL BOARDS

If the external board is a master on the bus, then it must receive and analyze the signal I/O CH RDY when it performs access cycles to other resources. When the external board is operating in other modes, it must enable this signal when it is ready to complete the cycle.

I/O CH RDY and perform all access cycles as normal 8- or 16-bit memory access cycles. Therefore, when installing an external board into a computer, which requires an extension of the signal access cycle I/O CH RDY, you should definitely make sure that there is no such incorrectly designed external board in your computer.

-0WS

Signal -0WS(0 Wait States - 0 wait cycles) is the only signal on the entire bus that requires synchronization with the frequency when received by the master on the bus SYSCLK. It is enabled by the resource being accessed by the CPU or external board and informs the master on the bus that the access cycle must be completed without inserting a wait clock.

NOTE: Although this signal is attached to an 8-bit card slot, it cannot be used by an 8-bit resource. It can only be used when accessing 16-bit memory installed in a slot when the CPU or external board is the master on the bus. This signal is ignored when accessing the air source or when the DMA controller or regeneration controller is a master on the bus.

FEATURES FOR EXTERNAL BOARDS

If the external board is a master on the bus, then it must receive the signal -0WS from the resources it accesses and perform access cycles on those resources without additional wait cycles. When the external board is 16-bit memory, then it must enable the signal -0WS, if the speed of this memory allows you to perform access cycles without inserting an additional wait cycle.

ATTENTION! Unfortunately, some external boards, having become a master on the bus, ignore the signal -0WS and perform all access cycles as normal 8- or 16-bit memory access cycles.

-REFRESH

Signal -REFRESH(Refresh) is enabled by the refresh controller to inform all devices on the bus that memory refresh cycles are in progress.

FEATURES FOR EXTERNAL BOARDS

If the external board is a master on the bus, then it must enable the signal -REFRESH for a memory regeneration request. In this case, the regeneration cycle will be executed even though the regeneration controller is not a master on the bus.

4.3. Central control signals

The group of central control signals consists of signals of various frequencies, control signals and errors.

Signal -MASTER(Master) must be generated only by the external board that wants to become a master on the bus.

ATTENTION! If the signal -MASTER enabled for a time greater than 15 µs, then the external board must request a memory refresh cycle by enabling the signal -REFRESH.

FEATURES FOR EXTERNAL BOARDS

Signal -MASTER allowed by an external board that becomes a master on the bus, only after it receives the corresponding signal -DACK from the DDP controller. After the signal -MASTER will be enabled, the external board must wait at least one frequency period SYSCLK, before starting to generate address and data signals and a minimum of two periods SYSCLK before the generation of command signals.

-I/O CH CK

Signal -I/O CH CK(I/O Channel Check) can be resolved by any resource on the bus as a fatal error message that cannot be corrected. A typical example of such an error is a parity error during memory access. Signal - I/O CH CK must be enabled for a time of at least 15 ns. If at the time of generation of this signal the master on the bus was a DMA controller or a regeneration controller, then the signal -I/O CH CK will be written to a register on the motherboard, and processed only after the central processor becomes a master on the bus.

This signal is usually connected to the non-maskable interrupt input of the CPU and its generation causes the computer to stop normal operation.

FEATURES FOR EXTERNAL BOARDS

If the signal -I/O CH CK is enabled at the moment when the master on the bus is an external board, it is written to a register on the motherboard and will be processed only after the bus is captured by the central processor.

RESET DRV

Signal RESET DRV(Reset Driver) is generated by the central processor to initially set up all access resources on the bus after the power is turned on or its voltage drops. The minimum resolution time for this signal is 1 ms.

FEATURES FOR EXTERNAL BOARDS

External boards must switch their outputs to the third state for the entire time this signal is generated.

SYSCLK

Signal SYSCLK(System Clock - system frequency) in this book is assumed to be 8 MHz, although, as a rule, this frequency is the same as the clock frequency of the central processor on the motherboard, but with 50% (by duration) of the logical "1" level. All bus cycles are proportional SYSCLK, but all signals on the bus except -0WS, not synchronized with SYSCLK.

FEATURES FOR EXTERNAL BOARDS

When the external board is a bus master, it can use SYSCLK to set the cycle length, but other than generating -0WS, any synchronization signal can be used.

O.S.C.

Signal O.S.C. generated by the motherboard always at a fixed frequency of 14.3818 MHz with 45-55% (in duration) at the logical level “1”. Signal O.S.C. not synchronized with any SYSCLK with any other signal on the bus and therefore cannot be used for applications requiring synchronization with other signals. Historically, this signal appeared to support the first color monitor controllers for personal computers of the IBM PC series. This signal is convenient for use with external cards because it is the same for all IBM PC/AT compatible computer models.

4.4. Interrupt signals

The interrupt signal group is used to request an interrupt to the CPU.

NOTE: Interrupt request signals are typically attached to an Intel 8259A type interrupt controller. Despite the fact that any master on the bus has access to interrupt controllers (as to UVV), for software compatibility only the central processor can service the interrupt controller.

IRQ<15,14,12,11,10> IRQ<9,7...3>

An interrupt can be requested by resources both on the motherboard and on external boards by resolving the corresponding signal IRQ. The signal must remain enabled until the interrupt is acknowledged by the CPU, which typically involves the CPU accessing the resource that requested the interrupt.

FEATURES FOR EXTERNAL BOARDS

An interrupt request is written to a trigger in the interrupt controller on the rising edge of the interrupt request signal and must be generated by microcircuits with conventional TTL outputs. Therefore, when selecting an interrupt request line for your external card, you should make sure that this line is not occupied by any other external card.

4.5. DMA mode signals

These signals support data transfer cycles during direct memory access.

NOTE: DMA channels<3...0>only support 8-bit data transfers. DDP channels<7...5>support transfers of 16-bit data only.

DRQ<7...5,0> DRQ<3,2,1>

Signals DRQ(DMA Request) are resolved by resources on the motherboard or external boards to request service by the DMA controller or to seize the bus. Signal DRQ must be enabled until the DMA controller enables the corresponding signal -DACK.

FEATURES FOR EXTERNAL BOARDS

Signals DRQ are generated from the outputs of conventional TTL microcircuits, therefore, when installing an external board in an ISA bus slot, you should correctly select the DMA channel, which should not be occupied by other external boards.

-DACK<7...5,0> -DACK<3,2,1>

Signals -DACK(DMA Acknowledge - DMA confirmation) are allowed by the DMA controller as confirmation of request signals DRQ<7...5,3...0> . Resolution of the corresponding signal -DACK means that either DMA cycles will be started or the external board has captured the bus.

T/C

Signal T/C(Terminal Count) is enabled by the DDP controller when the count of the number of data transfers is completed on any of the DMA channels, that is, all data transfers are completed.

4.6. Nutrition

To power external boards on the bus ISA 5 supply voltages are used direct current: +5 V, -5 V, +12 V, -12 V, 0 V (case - Ground). All power lines are connected to the 8-bit connector, except for one +5 V line and one body line on the additional connector.

Maximum permissible currents consumption for the external board for each supply voltage is given in table. 4.1.

Table 4.1. Maximum current consumption by external board

Voltage

ATTENTION! The data given in table. 4.1 do not mean that each of the external cards installed in the slots can consume such currents. The table only informs you what currents are allowed to pass through the connector(s) of the external board. The total permissible current consumption for all external cards is usually limited by the computer's power supply. Therefore, before installing a new external card in the bus slot, you should determine whether there is an appropriate reserve for current consumption for this card at the computer's power supply.

5. Bus cycles

Bus cycles ISA always asynchronous with respect to SYSCLK. Various signals are enabled and disabled at any time; within permissible intervals, response signals can also be generated at any time. The only exception is the signal -0WS, which must be synchronized with SYSCLK.

There are 4 individual cycle types on the bus: Access to the Resource, RAP, Regeneration, Tire Capture. Cycle Access to the Resource is executed if the central processor or external board as masters communicates with various resources on the bus. The DMA cycle is executed if the DMA controller is a master on the bus and performs data transfer cycles between the memory and the airborne device. The Regeneration cycle is performed only by the Regeneration controller to regenerate the dynamic memory chips. The Bus Capture cycle is performed by an external board to become a master on the bus.

Structurally, the cycles differ in the type of master on the bus and the types of access resources on it. Within a loop type there are different kinds it, due to the different duration of each type.

There are three types of cycle Access to the Resource:

a cycle with 0 wait cycles - this cycle is the shortest of all possible;

normal cycle - when performing such a cycle, the access resource does not prohibit the ready signal I/O CH RDY- henceforth a cycle of this type will be simply called normal;

extended cycle - when executing such a cycle, the access resource disables the ready signal I/O CH RDY for the time required for the resource to receive or transmit data - henceforth a cycle of this type will be called extended.

In the PDP and Regeneration cycles, there are also two types: normal and extended, based on the same conditions described above. Below, all types of cycles will be described in detail and, in addition, in Chapter. Figure 6 shows timing diagrams of all types of cycles.

5.1. Resource Access Cycle

The CPU begins the cycle Access to the Resource signal generation BALE, informing all resources about the truth of the address on the lines S.A.<19...0> , as well as for fixing addresses by resources along lines L.A.<23...17> . Resources must tell the CPU the resolution of the signal -MEM CS16 or -I/O CS16 that the cycle must be 16-bit; otherwise the loop will end as 8-bit. The CPU also issues instructions -MEMR, -MEMW, -IORC And -IOWC defining the type of resource (memory or airwave), as well as the direction of data transfer. If the memory is accessed in the first megabyte of the address space, then the signal will also be resolved -SMEMR or -SMEMW. An access resource that needs to change its cycle time must respond with a signal -0WS or I/O CH RDY to inform the CPU about the duration of the access cycle.

FEATURES FOR EXTERNAL BOARDS

The external board that has captured the bus also begins the access cycle by generating address signals, but, unlike the CPU, does not confirm the address with a signal BALE. On the line of this signal, the motherboard maintains a logical level of “1” for the entire time the bus is captured by the external board. Therefore, the external board must produce true signals both along the lines S.A.<19...0> and along the lines L.A.<23...17> before the command signals begin to be enabled, maintaining the address until the end of the cycle. The external board must also be capable of signal analysis -MEM CS16 And -I/O CS16 and, in accordance with these signals, terminate the loop as 16- or 8-bit.

5.1.1. Resource Access Cycle - 0 wait cycles

An access cycle with 0 wait cycles is the shortest cycle possible on the bus. This loop can only be executed when the CPU or external board (when it is a master on the bus) is accessing 16-bit memory. At the beginning of the cycle, the master must set the address on the lines L.A.<23...17> to select a 128 KB memory block. If the signal is then not allowed -MEM CS16, then the loop will terminate as an 8-bit (normal or extended) and the loop with 0 wait cycles will not be executed. If the resource allows the signal -MEM CS16, then it must enable the signal -0WS at the appropriate time after the command signal is issued -MEMR or -MEMW to end the loop with 0 wait cycles. When the signal is prohibited -0WS the cycle ends as normal or extended.

NOTES: If the signal -0WS is allowed by the access resource, then the master does not require signal permission I/O CH RDY- he is ignored. Signal only -0WS is on the bus ISA synchronous with respect to SYSCLK signal.

FEATURES FOR EXTERNAL BOARDS

The external board that has taken over the bus performs an access cycle with 0 wait cycles just like the central processor.

5.1.2. Resource Access Cycle - Normal Cycle

A normal loop can be executed by the CPU or an external board (if it owns the bus) when accessing an 8- or 16-bit device or memory. After issuing address signals to the bus, the master enables command signals -MEMR, -MEMW, -I/OR or -I/OW. In response, the resource must resolve the signal I/O CH RDY at the appropriate time, otherwise the cycle will end as an extended one. Permission I/O CH RDY forces the master to complete the cycle in a fixed period of time (this period is a multiple of the period SYSCLK, but is not synchronized with it). The duration of the normal cycle is determined by the signal resolution time -MEMR, -MEMW, -I/OR or -I/OW which, in turn, depends on the size of the data and the address of the access resource.

5.1.3. Resource Access Cycle - Extended Cycle

An extended loop can be executed by the CPU or an external board (if it owns the bus) when accessing an 8- or 16-bit device or memory. The bus master executes an extended loop if the resource being accessed does not enable the signal at the appropriate time after the command signal is enabled. I/O CH RDY. The master continues to enable the command signal until the resource allows the signal I/O CH RDY. The time period of the extended cycle is also a multiple SYSCLK

5.2. Regeneration Cycle - Introduction

The regeneration controller attempts to seize the bus after 15 µs has elapsed since the last regeneration cycle in two ways:

if the bus is owned by the central processor, then upon completion of the current command it transfers the bus to the regeneration controller;

if the bus is owned by the DMA controller, then the bus will be transferred to the regeneration controller only after the completion of data transfer cycles by the DMA controller.

The purpose of the following signals during the regeneration cycle has an original interpretation:

-REFRESH- the resolution of this signal indicates the beginning of the regeneration cycle;

Address- the regeneration controller generates only signals via the SA address lines<7...0>, the remaining address signals are not defined;

-MEMR- signal -MEMR enabled by the regeneration controller, while the -SMEMR signal will be enabled by the motherboard;

SD<15...0> - data lines are ignored by the regeneration controller and all resources on the bus are required to transfer their outputs via data lines to the third state;

These signals are ignored by the regeneration controller:

-MEM CS16

-I/O CS16

FEATURES FOR EXTERNAL BOARDS

When the external board is a master on the bus, it must independently enable the signal -REFRESH to start the memory regeneration cycle.

5.2.1. Regeneration Cycle - Normal Cycle

The normal regeneration cycle is started by the regeneration controller by enabling the signal -MEMR, in response the resource must resolve the signal I/O CH RDY at the appropriate time, otherwise the cycle will end as an extended one. The cycle length is actually determined only by the duration of the signal -MEMR.

5.2.2. Regeneration Cycle - Extended Cycle

The regeneration controller performs an extended cycle if at least one access resource does not allow the signal I/O CH RDY at the appropriate time after signal resolution -MEMR. The regeneration controller continues to enable the signal -MEMR before the signal I/O CH RDY will be enabled by all resources on the bus. The time period of the extended cycle is also a multiple SYSCLK, but is not synchronized with it.

5.3. DAP cycle

The DMA cycle is similar to the access cycle performed by another bus owner. DMA cycles are started after the signal is enabled -DACK DDP controller. The size of the data transferred depends on the DMA channel used: channels 0 to 3 are defined for 8-bit data transfers, and channels 5 to 7 are defined for 16-bit data transfers. Signals -MEM CS16 And -I/O CS1 6 are ignored by the DMA controller itself, but these signals are used by the byte shuffler on the motherboard.

DMA cycles are performed only between memory and I/O devices. The address signals generated by the DMA controller contain only the memory address and do not contain the airborne address. The process of sending data in a DMA cycle works like this: the data source puts data on the bus, and the data receiver must be ready to receive it at the same time. Write and read commands are also allowed simultaneously for the right choice forwarding directions. In this case, the read signal is necessarily enabled before the write signal to avoid a collision between the data buffers in the two resources.

The airborne device requesting the DMA mode on the bus allows the signal DRQ the corresponding channel. If the master on the bus is the central processor, then it releases the bus to the DMA controller, which, in turn, notifies the airborne controller with the signal permission -DACK that the RAP cycle begins. Since the DMA controller produces only the memory address, the airborne device must use signals -I/OR, -I/OW And -DACK for receiving or transmitting data in DMA mode.

The DMA cycle begins with signal enable -DACK the corresponding channel, as well as the signal AEN. Signal resolution AEN The DMA controller notifies all resources on the bus that the addresses and command signals are generated by the DMA controller and not by the central processor, regeneration controller, or external board. After the command signals are resolved, the DMA controller analyzes the signal I/O CH RDY to determine the cycle duration.

If the cycle lengthens, then the lengthening period is a multiple of twice the period SYSCLK, although not synchronized with SYSCLK.

NOTE: Data that is written to memory or the airborne device must be true before the write command is enabled and remain true until the write command is disabled.

5.3.1. TAP cycle - Normal cycle

The normal loop is performed by the DMA controller for 8- or 16-bit data transfers. DMA controller enables signals -MEMR, -MEMW, -I/OR And -I/OW, and the memory with which the exchange is performed must allow the signal I/O CH RDY at the appropriate time, otherwise the cycle will end as extended. Signal resolution I/O CH RDY causes the controller to complete a loop in a fixed period of time; this period is a multiple of the period SYSCLK, but is not synchronized with it.

Signal resolution duration -MEMR, -MEMW, -I/OR And -I/OW determines the duration of the entire cycle, and this duration depends on the data size for different address spaces.

5.3.2. DAP Cycle - Extended Cycle

The extended DMA cycle is executed by the DMA controller in the same way as the normal cycle, except that in the extended cycle the signal I/O CH RDY is not enabled at the appropriate time after the command signal is enabled. The DPM controller continues to allow command signals until the airborne device allows the signal I/O CH RDY. The period of time by which the cycle is extended is in this case a multiple of twice the period SYSCLK, although not synchronous with SYSCLK.

NOTE: Address Signals L.A.<23...0> during a normal access cycle must be written to a register by access resources to remember the address throughout the entire cycle. Unlike normal loops, when executing DMA loops, these address signals are true for the entire DMA loop.

ATTENTION! DMA channels that are used by external cards to capture the bus must be programmed in cascade mode.

5.4. Tire Pickup Cycle

Any external card installed in the slot can become a master on the ISA bus. Bus capture external board must start with signal enable DRQ DMA channel pre-programmed in cascade mode. A DMA channel programmed in cascade mode assumes that all DMA cycles have been executed by an external resource - in this case, an external board. The DMA controller responds to the external board with signal resolution -DACK; external board in response to -DACK allows the signal -MASTER. After signal resolution -MASTER the external board must wait for some time before it can begin its access cycles.

6. ISA bus timing diagrams

The tables in this chapter show the timing relationships for all the cycles explained in the previous chapter. All times are given for a frequency of SYSCLK = 8 MHz, therefore, if the designed external board must operate in computers with a SYSCLK frequency of up to 16 MHz, then the requirements for the speed of the external board should be tightened by at least twice as much as those given. For resources, all times are measured at the access resource connector. Time in the range of 0...11 ns is added to take into account the signal propagation time along the bus. In some cases, the signal is returned from the resource that was the source of the signal synchronized with the one being returned, in which case 0...22 ns is added. Time "0" means the theoretically minimum possible time and is used only as an estimate when determining the cycle time.

NOTE: The tables and timing diagrams show only the -MEMR and -MEMW signals, not the -SMEMR and -SMEMW signals. The -SMEMR and -SMEMW signals are generated with a delay of 0 to 10 ns relative to the -MEMR and -MEMW signals in cases where the CPU, DMA controller or regeneration controller is a master on the bus. If the master on the bus is an external board, then the delay can be increased to 22 ns.

NOTE: In all timing tables, TCLK denotes the bus clock period.

Table 6.1. Timing relationships for cycles with 0 wait cycles, normal and extended, for 16- and 8-bit memory resources and airwaves.

N parameter	Name	Bus master (ns)		Access resource (ns)
			Max		Max
	L.A.<23...17>set to BALE
	Pulse width BALE
	L.A.<23...17>saved after BALE
	L.A.<23...17>
	MEM CS16 true from LA<23...17>
	MEM CS16 is held after LA<23...17>
	S.A.<19...0>set before command for 16-bit memory
	S.A.<19...0>set before command for 16- or 8-bit airwave
	SBHE is set before the command for 16-bit memory
	SBHE is set before the command for 16- or 8-bit airwaves
	Duration of write/read commands when accessing 16-bit memory (normal or extended cycle)
	Duration of write/read commands when accessing 16-bit airwaves (normal or extended cycle)
	Duration of write/read commands when accessing 16-bit memory (0 wait cycles)
	Duration of write/read commands when accessing 8-bit resources (normal or extended cycle)
	S.A.<19...0>set to BALE
	Data settling time after 16-bit memory read signal
	Data settling time after 16-bit UVV read signal
	Data settling time after 16-bit memory read signal for a cycle with 0 wait cycles
	d Data settling time after 8-bit read signal
	Data settling time in a 16-bit memory write cycle
	Data establishment time in a write cycle to a 16-bit airwave
	Settling time for data in a write cycle to an 8-bit resource
	S.A.<19...0>, -SBHE are removed after the command signal
	Command shutdown time when accessing a 16-bit resource
	Command shutdown time when accessing an 8-bit resource
	Read data settling time before command is removed
	Holding data while reading
	Data retention while writing
	Translation of SD signals<15...0>to the third state after the command is removed
	0WS true from command
	I/O CS16 true from SA<19...0>
	I/O CS16 is held after SA is removed<19...0>
	I/O CH RDY to log "0" from a 16-bit command
	I/O CH RDY to log "0" from 8-bit command
	I/O CH RDY duration in log."0" TCLK
	Removing the command signal after enabling I/O CH RDY
	Allowing BALE after command is cleared
	Clock period (TCLK)
	Data is set before I/O CH RDY is enabled
	L.A.<23...17>held after memory access command is enabled
	Duration -0WS
	0WS is set before SYSCLK falls
	0WS is held after SYSCLK falls

Note: (1)LA<23...17>are produced in the same way as SA<19...0>, if the master on the bus is not the central processor.

Table 6.2. Time relationships for the memory regeneration cycle.

N parameter	Name	Regeneration controller (ns)		External board (ns)
			Max		Max
	Duration -MEMR/-SMEMR
	S.A.<19...0>pre-MEMR installed
	S.A.<19...0>held after command completion
	I/O CH RDY to log."0" from -MEMR/-SMEMR
	MEMR is cleared after I/O CH RDY is enabled
	REFRESH is set to -MEMR
	REFRESH is held after disabling -MEMR (1)
	S.A.<19...0>and -MEMR are held in the third state after -MEMR is inhibited
	Delay for returning bus control after disabling -REFRESH

NOTE: (1) The -REFRESH signal can be held for a long time to perform multiple memory refresh cycles.

Table 6.3. Timing relationships for DMA cycles

N parameter	Name	External board as source or DMA controller (ns)		External board as receiver (ns)
		Min	Max	Min	Max
	DACK, AEN are set to -I/OR, -I/OW
	The address is set before the command
	I/OR is set to -MEMW
	MEMR is set to -I/OW
	Data is set from -I/OR(1)
	Data is set from -MEMR(1)
	Data is set to resolution -MEMW
	Data is set to -I/OW resolution
	Read command is held after write command is disabled
	Address is withheld after commands are prohibited
	Data held after commands are disabled(1)
	I/O CH RDY to log "0" from the memory access command (1)
	T/C is set before the command
	T/C is withheld after command is prohibited
	Duration -I/OR
	Duration -MEMR
	Duration -I/OW
	Duration -MEMW
	DACK is held after command is disabled
	AEN is held after command is inhibited
	DRQ active from command enable
	Duration log."0" I/O CH RDY

NOTE: (1) Not for DMA controller, but for external board.

Table 6.4. Timing Relationships for the Bus Pickup Cycle

N parameter	Name	CPU, DMA controller, regeneration controller (ns)		External board (ns)
		Min	Max	Min	Max
	DACK is enabled after DRQ is enabled (1)
	Delay -MASTER from -DACK 0
	The DMA controller moves its outputs to the third state
	AEN is held after -MASTER is enabled
	The external board begins to produce address, data and command signals
	-MASTER signal is held after DRQ is disabled
	-DACK signal held after DRQ inhibit (2)
	The external board moves its outputs to the third state until the -MASTER signal is disabled
	The CPU begins to generate its signals after the -MASTER signal is disabled
Rice. 6.5. Normal and extended write/read cycle of an 8-bit I/O device Rice. 6.6. Normal and extended regeneration cycle: 1 - The resolution time of the -REFRESH signal can be increased to perform several regeneration cycles; 2 - The current master on the bus must transfer the address and command signals to the third state before the REFRESH signal is enabled. Rice. 6.7. Normal and extended DAP cycles: 1 - DRQ can become negative at any time after -DACK; 2 - IO/CH RDY is disabled to insert additional wait clocks. Each additional wait clock cycle consists of two SYSCLK clock cycles; 3 - The DMA controller activates the TC signal during the last data transfer Rice. 6.8. Bus capture cycle: (1) - DMA controller; (2) - External board 7. Characteristics of bus connectors 7.1. Pin assignment of connectors installed in slots The connector pin assignments are shown from top to bottom (with the external board installed, the component side corresponds to the right half of the connectors, and the mounting strip location corresponds to the top). 36-pin connector: Housing (GND) Housing (GND) SA14 Housing (GND) 7.2. Electrical characteristics of signals The abbreviations disclosed below will be used later when discussing signal performance requirements on the bus. THREE - three-state output. Has states: active low level, active high level, off; OK - open collector output. Has states: active low level, off; TTL - output of transistor-transistor logic with two states. Has states: active low level, active high level; Iih - high level input current. This current occurs when an active high output is connected to the input; Iil - low level input current. This current occurs when an active low output is connected to the input. Ioh - high level output current. Characterizes the load capacity of the device output in the active high level; Iol - low level output current. Characterizes the load capacity of the device output at an active low level; Vih - high level input voltage; Vil - low level input voltage; Voh - high level output voltage; Vol - low level output voltage. Voltages and currents along signal circuits on the bus. Only three types of devices can be used on the ISA bus: TTL (transistor-transistor logic), TRI (tristable) and OK (open collector output). A TTL device can only be of a fixed direction - either input or output. A three-state device can be both an input and an output, and in addition, be in a third state. transmitter receiver transmitter receiver transmitter NOTES: (1) Voh=2.4 V Vih=2.7 V Vol=0.5 V Vil=0.4 V All currents in the table are indicated in milliamps. The "-" sign before the current value means that the current flows from the external board to the motherboard cross-connect. (2) Open collector output line can be connected to TTL input. (3) On a line with an open collector output, the current Ioh (leakage current) should not exceed 0.4 milliamps for each slot. 7.4. Additional requirements for receivers and transmitters on external boards Developing your own external boards requires compliance with a number of conditions, in addition to those specified in the table. 7.4. These are the following conditions: when designing a printed circuit board topology on an external board, it should be taken into account that the maximum length of the printed conductor from the connector contact to the output of the component connected to this circuit should not exceed 65 mm; To minimize noise on the bus and reduce reflections, you should use components with a rise/fall slope of the output voltage of at least 3 ns. The maximum capacitance for each pin of the interface connector should be no more than 20 pF. This capacitance includes the input capacitances of all receivers and transmitters connected to the pin, and, in addition, the capacitance of the printed conductor connecting the connector pin to the components. Table 7.2. Resistor values ​​and connection method Consistently 7.5. Bus load resistors Load resistors are installed on the motherboard cross-connect to optimize the electrical characteristics of the bus. Load resistors are connected in two ways: between signal line and +5 V; in series between the resource on the motherboard and the signal line on the bus. 7.6. Mechanical characteristics of external board When designing an external board, you should also consider the following: the thickness of the board should be 1.6 mm +- 0.2 mm (taking into account the thickness of the foil); board warpage should not exceed 1.3 mm over the entire board length; The maximum height of components on the board is no more than 10 mm.

Introduction 3

1 Topic analysis course work 4

1.1 Analysis of existing devices and their design features 4

1.2 ISA 9 system bus

1.2.1 System bus characteristics 9

1.2.2 Design features of system bus modules 19

1.3 Module 22 design stages

1.4 Conclusions to Chapter 1 22

2 Development of module diagram 23

2.1 General information 23

2.2 Development of a generalized scheme of module 24

2.3 Selection of VLSI and description of its structure 25

Description of operating modes of VLSI KR580VI53 27

2.4 Selecting the address space of I/O ports 28

2.5 Development of module interface elements 29

2.6 Selection of element base and development schematic diagram 30

2.7 Conclusions to Chapter 2 30

3 Development of software modules 31

3.1 Development of a software initialization module 31

3.2 Conclusions to Chapter 3 32

Conclusion 33

Appendix A
(reference) 34

Bibliography 34

Appendix B
(Required) 35

Appendix B
(Required) 36

State educational institution of higher education

vocational education

VYATSK STATE UNIVERSITY

FACULTY OF AUTOMATION AND COMPUTER ENGINEERING

DEPARTMENT OF AUTOMATION AND TELEMECHANICS

ASSIGNMENT FOR A COURSE PROJECT

in the discipline "Computer Architecture"

TOPIC: Development of hardware and software modules for the system busIsa

Student groups (cipher)

Initial data for the project: Option No. 15

●Perform a thematic review based on scientific and technical literature.

●Design VLSI based hardware module for ISA system bus.Programmable digital signal generator

●Develop software procedures for initialization, management and control of the hardware module.

Explanatory note:

Introduction

1 Analysis of the topic of course work Error: Cross reference source not found

1.1 Analysis of existing devices and features of their design Error: Cross reference source not found

1.2 System busISA 8

1.2.1 System bus characteristics Error: Cross reference source not found

1.2.2 Design features of system bus modules Error: Cross reference source not found

1.3 Module design stages Error: Cross reference source not found

1.4 Conclusions to Chapter 1 Error: Cross reference source not found

2 Development of the module diagram Error: Cross reference source not found

2.1 General information Error: Cross reference source not found

2.2 Development of a generalized module diagram Error: Cross reference source not found

2.3 Selection of VLSI and description of its structure Error: Cross reference source not found

2.4 Selecting the address space of I/O ports Error: Cross reference source not found

2.5 Development of module interface elements 27

2.6 Selection of element base and development of a circuit diagram 28

2.7 Conclusions to Chapter 2 28

3 Development of software modules 29

3.1 Development of a software initialization module 29

3.2 Conclusions to Chapter 3 30

Conclusion Error: Cross reference source not found

Appendix A (reference) Bibliography 32

Appendix B (Mandatory) List of abbreviations Error: Cross reference source not found

Appendix B (Required) Listing of the initialization software module Error: Cross reference source not found

Course work schedule:

1 Theoretical part 25% to _______ 3 Program part 25% to _______

2 Calculation part 25% to _______ 4 Graphic part 25% to _______

Work manager _____________/_____________________/ 02/17/2010

(signature) (Teacher’s full name)

Accepted the task by _____________/_____________________/ 02/17/2010

(signature) (student's full name)

Introduction

Recently, discrete control systems and discrete information transmission systems have become widespread. The operation of such systems is based on discrete (digital) information processing and discrete (digital) signals, which are described by sequences of reference values ​​in a discrete set of points.

Digital signals have a number of advantages over analogue ones. Unlike analog, digital signals are not transmitted as waves, but in binary form, or in the form of bits. The presence of voltage is indicated as one, and the absence - as zero. This property of the digital format, in which only two states are provided - there is a signal and there is no signal - allows you to receive and reproduce sounds in their pristine purity. With digital signals this can be done with a high degree of reliability. It is much more difficult to accurately reproduce a wave capable of receiving the most different shapes, unlike a bit, which can only have two values ​​- on and off.

Both analog and digital signals are inherently unstable during transmission. As the propagation range increases, both signals weaken, attenuate, and are subject to interference. However, digital signals can be corrected and restored better than analog signals. When a digital signal exposed to interference begins to fade, the device on the communication line designed to amplify it, “knowing” that each bit of information is either a one or a zero, restores the signal without distortion. The interference is discarded rather than regenerated and amplified, as is the case with an analog signal.

In addition to the purity of audio signals, digital signals allow data to be sent with fewer errors. In analog lines, where the noise signal is also amplified, receiving devices can interpret this signal as a bit of information. Those who use modems to exchange data often receive corrupted information. In digital communications, the interfering signal is discarded and therefore distortions and errors in data transmission are observed less frequently.

This course project is devoted to the development of one of these modules - a programmable digital signal generator, that is, a rectangular pulse generator. The required maximum output frequency according to the specification is 2 MHz, the number of outputs is 1.

The design process is divided into a number of stages. Chapter 1 analyzes the topic of the course work, examines existing analogues of the projected module and the features of their design, and provides characteristics of the ISA bus. Chapter 2 discusses the design features of the module, the choice of VLSI, address space, and develops a circuit diagram. Chapter 3 describes the development of the device initialization software module.

1 Analysis of the topic of course work

1.1 Analysis of existing devices and features of their design

A digital signal is a signal that can only take one of two specified states. In most circuits, it is accepted that the appearance at the output of an electrical circuit of a voltage ranging from 2.4V to 5V corresponds to the appearance of a single signal (high level of the digital signal), if the voltage does not exceed 0.5V, then the signal is taken equal to 0 (low level of the digital signal ).

It is necessary to develop a programmable digital signal generator with 1 output, that is, in fact, a square pulse generator.

The maximum frequency of the output signal is 2 MHz. By programmability we mean the ability to set signal parameters. Two parameters completely determine the shape of a rectangular pulse: frequency and duty cycle. Graphically the above values ​​are presented in Fig. 1.1.

Rice. 1.1 – Digital signal, its characteristics

Such a generator can be used:

In a control and measuring system based on a personal computer.

To generate clock signals.

As part of industrial installations that require the generation of various signals.

For operation as part of automated complexes for searching for listening devices (RS/N and RS/N232 generators).

The RV131.03 generator is designed to generate a time interval and a pulse series with equal programmable duration, as well as to generate logical signals marking the beginning and end of the set duration of the time interval and to convert the processes under study into digital form.

Generation of digital television test signals G-420, TG 2000, DTG-35, G-230, G6-35.

The generator can be developed as a module containing a buffer RAM, where sample codes of the generated signal are written, specifying, in particular, its frequency and duty cycle. Then the generator starts. There are also generators with two starting modes:

one-time start mode (generation stops after one signal period);

mode automatic start(continuous generation until it is stopped by software.

Let's consider what signals and data should arrive at the system input. The input receives a frequency code, a duty cycle code, as well as two control bits: generation permission/inhibition and one-time/automatic start. In addition to the digital signal itself, the module must also produce a “generation in progress” signal, which is necessary for control and indication.

Two approaches are used to set the frequency:

1. The addresses of the buffer RAM are enumerated with a conventional binary counter, and to change the frequency of the output signal, the frequency with which these addresses are enumerated is changed. In this case, all RAM addresses are always polled, i.e. the number of samples per period of the output signal does not change when the frequency changes, which means that the accuracy of the signal shape reproduction does not change. The disadvantages of this approach are that the scheme works well in low frequencies output signal and the fact that the frequency of the interference signal arising from the quantization of the output signal levels is directly proportional to the frequency of the output signal, filtering such interference is complex and requires special tunable filters.

2. To enumerate the addresses of the buffer RAM, not a counter is used, but an accumulating adder (Fig. 1.2, Fig. 1.3), consisting of a binary adder and a register covered by feedback. In this case, with each subsequent pulse of the clock generator, the input control code is added to the output code of the register and the resulting amount is again written to the register. As a result, in each clock cycle the increment of the RAM address will be determined by the input control code of the accumulating adder, by changing which we can change the speed of passage of all RAM addresses, and therefore the signal frequency. The disadvantage of this approach is that the signal shape is reproduced with different accuracy at different frequencies. The advantage of this approach is that the frequency of the interference signal will be constant and it is easier to filter out such interference.

Rice. 1.2 - Enumerating RAM addresses using an accumulating adder

There are many fundamentally different ways to construct various pulse generators. Let's consider the construction of such devices based on elementary logical elements.

1) The generator presented in Figure 1.4 (using 2I-NOT elements with an open collector) produces pulses in a wide range of frequencies - from a few hertz to several kilohertz. Dependence of frequency f (kHz) on capacitance

capacitor C1 (pF) is expressed by the approximate formula
. The duty cycle of the pulse voltage is almost equal to 2. When the power supply voltage decreases by 0.5 V, the frequency of the generated pulses decreases by 20%.

Rice. 1.4 – Pulse generator on the K155LA8 chip

2) A wide change in the frequency of the generated pulses (about 50 thousand times) is provided by the device below (Fig. 1.5). The minimum pulse frequency here is about 25 Hz. The duration of the pulses is regulated by resistor R 1. The repetition frequency can be determined by the formula:

Rice. 1.5 - Pulse generator with adjustable duration

3) The duration of the pulses can be adjusted with a variable resistor R 2 (the duty cycle varies from 1.5 to 3), and the frequency with resistor R 1 (see Fig. 1.6). For example, in a generator with C 1 = 0.1 μF, by excluding resistor R 2 only resistor R 1, the frequency of the generated pulses can be changed from 8 to 125 kHz. To obtain a different frequency range, it is necessary to change the capacitance of capacitor C 1.

Rice. 1.6 – Pulse generator with adjustable duration

4) When implementing digital devices for various purposes, it is often necessary to generate short pulses along the edges of the input signal. In particular, such pulses are used to reset counters as synchronization pulses when writing information to registers, etc. When the voltage Uin changes from low to high, this drop is supplied without delay to input 13 of element DD1.4. At the same

time at input 12 of element DD1.4, the high level voltage is maintained during the time of signal propagation through elements DD1.1-DD1.3 (about 75 ns). As a result, during this time the device output voltage remains low. Then the voltage is set to low at input 12, and high at the output of the device. Thus, a short negative pulse is formed, the front of which coincides with the front of the input voltage. In order to use such a device to generate a negative pulse at the cutoff of the input signal, it must be supplemented with another inverter. The diagram and timing diagrams of the operation of such a device are presented in Fig. 1.7.

Rice. 1.7 – Circuit and timing diagrams of a short negative pulse generator based on a positive/negative voltage drop at its input

Figure 1.8 shows the circuit and timing diagram of the operation of the pulse shaper along the leading edge and falling edge of the input signal.

Rice. 1.8 Pulse former on the edge and fall of the input signal

5) The problem of generating a digital signal of a given frequency and duty cycle can also be solved using single vibrators (Fig. 1.9). The K155 series also includes the K155AG3 microcircuit. The timing diagrams of its operation are presented in Fig. 1.10. It contains two monovibrators in one housing. Options for connecting external timing elements and the timing diagram of the monovibrator are shown in the figures. The monostable is also triggered either by a negative drop in the input signal at input A with a high level at inputs B and R, or a positive drop in voltage at input B with a low level at input A and a high level at input R. The pulse duration t and1 is determined by the time constant of the timing circuit, but can be reduced by applying a low level voltage to the input R at t and2

Rice. 1.9 – Pulse shaper options using monostables

Rice. 1.10 – Timing diagram of the operation of the K155AG3 circuit

6) Digital signal generators can also be built using a specialized LSI. However, most problems of this kind can be solved using standard elements without using a microcontroller.

1.2 ISA system bus

1.2.1 System bus characteristics

System bus featuresISA

ISA (from the English Industry Standard Architecture, ISA bus, pronounced ay-say) is an 8 or 16-bit input/output bus for IBM PC-compatible computers. Used to connect ISA standard expansion cards. Structurally, it is made in the form of a 62 or 98-pin connector on the motherboard.

With the advent of ATX motherboards, the ISA bus has ceased to be widely used in computers, although there are ATX boards with AGP 4x, 6 PCI and one (or two) ISA ports. But for now it can still be found in old AT computers, as well as in industrial computers.

ISA was used in the first IBM PC in 1981, and in an enhanced 16-bit version in IBM PC/AT computers in 1984. Currently, the ISA bus has given way to the PCI bus and its graphics extension AGP. Moreover, AGP is already being replaced by the rather promising PCI-Express bus. However, in industrial and embedded high-performance computers this “ancient” ISA bus (along with EISA) is the main one. The reasons for this are as follows:

high reliability, broad capabilities, compatibility; This bus is faster than most peripheral devices connected to it.

the largest number of systems due to the low price;

a huge variety of applications;

transmission speed up to 2 Mbit/s;

good noise immunity;

a large number of compatible equipment and software (thanks to it, components from different manufacturers are interchangeable).

There are two versions of the ISA bus, differing in the number of data bits: 8-bit version (old) and 16-bit (new). Old version worked at a clock frequency of 4.77 MHz in PC and XT class computers. A new version used in AT class computers at clock frequencies of 6 and 8 MHz. Later, agreement was reached on a standard maximum clock speed of 8.33 MHz for both versions of the buses, ensuring their compatibility. Some systems allow the use of buses when operating at high frequencies, but not all adapter cards can withstand such speeds. It takes from 2 to 8 clock cycles to transmit data on the bus. You can determine the maximum data transfer rate on the ISA bus (it is 8 MB/s):

The bandwidth of the 8-bit bus is 2 times less (4 MB/s). These throughput values ​​are theoretical. In practice, it turns out to be approximately 2 times less than the theoretical one, but this does not prevent the ISA bus from working faster than most peripheral devices connected to it.

Distinctive features of the tire ISA :

1. A characteristic difference between ISA is that the clock signal does not coincide with the processor clock signal, therefore the exchange rate through it is disproportionate to the processor clock frequency.

2. The ISA bus refers to demultiplexed (i.e., having separate address and data buses) 16-bit medium-speed system buses. The exchange is carried out in 8- or 16-bit data.

3. Separate access to computer memory and input/output devices is organized on the highway (there are special signals for this).

4. The maximum amount of addressable memory is 17 MB (24 address lines).

5. The maximum address space for I/O devices is 64 KB (16 address lines), although almost all expansion cards available use only 10 address lines (1 KB).

6. The backbone supports dynamic memory regeneration, radial interrupts and direct memory access.

7. It is allowed to capture the highway by external devices.

8. Positive logic on address and data buses, i.e. One corresponds to a high voltage level, and zero corresponds to a low voltage level. 4 supply voltages: +5V, -5V, +12V and -12V.

9. The range of available memory addresses is limited by the UMA region (Unified Memory Architecture - a unified memory architecture. The range of I/O addresses is limited above by the number of address bits used for decryption, the lower limit is limited by the region of addresses 0-FFh reserved for system board devices. In the PC there was 10-bit I/O addressing was adopted, in which address lines A were ignored by devices. Thus, the address range of ISA bus devices is limited to the area 100h-3FFh, that is, a total of 758 addresses of 8-bit registers. Some areas of these addresses are also claimed by system devices Subsequently, 12-bit addressing (range 100h-FFFh) began to be used, but when using it, it is always necessary to take into account the possibility of the presence on the bus of old 10-bit adapters that will “respond” to the address with the corresponding A bits in the entire allowable area of ​​four ISA-8 bus subscribers can have up to 6 IRQ (Interrupt Request) lines at their disposal, for ISA-16 their number reaches 11. Bus subscribers can use up to three 8-bit DMA channels, and on a 16-bit bus they can three more 16-bit channels be available.

The most common design of the bus is connectors (slots) installed on the computer motherboard, all of whose contacts of the same name are connected to each other, i.e. All connectors are absolutely equal. A special feature of the backbone design is that expansion cards (daughter boards) connected to its connectors can have a variety of sizes (the length of the board is limited below by the size of the connector, and above by the length of the computer case).

8-bit busISA

This bus was used in the first IBM PC; it is practically not used in new systems. An adapter board with 62 gold-plated printed contacts is inserted into the connector. The connector is allocated 8 data lines and 20 address lines, which allows you to address up to 1 MB of memory. The adapter board for the 8-bit ISA bus has the following dimensions: height – 4.2″ (106.68 mm), length – 13.13″ (333.3 mm), thickness – 0.5″ (12.7 mm) . The pin assignments and connector of the 8-bit ISA bus are shown in Fig. 1.11.

Rice. 1.11 - Pin assignments and connector of the 8-bit ISA bus

The board selection signal –CARD SLCTD must be supplied to pin B8. The fact is that in XT-class computers and PC-class laptops, not all boards could be inserted into slot 8 (closest to the power source). For example, a keyboard/timer board from a 3270 PC could be inserted there. These boards have different synchronization requirements for this slot, provided by a special clock signal.

16-bit busISA

Appeared in PC/AT computers with dual expansion connectors. The 8-bit card can be inserted into the main part of the 16-bit connector. There are 2 features that make it impossible to insert the board into the connector the other way around:

key - a cutout in the adapter board, which, when installed, coincides or does not coincide with the protrusion on the connector.

different lengths of the two parts of the bus connector.

Additional contacts that appear due to an increase in the bus width are connected to 36 contacts of the second part of the connector. One or two contacts in the main part have a different purpose.

In some older adapters, part of the bottom edge, free of printed contacts, protrudes down and is used for installing elements or wiring

conductors. After installing such an adapter into the connector, this edge practically touches the surface of the motherboard. If there is an extension of the bus connector on this section of the motherboard, then it is impossible to insert the adapter. For such cards there are two connectors without 16-bit expansion.

A typical AT class adapter board has the following dimensions: height – 4.8″ (121.92 mm), length – 13.13″ (333.3 mm), thickness – 0.5″ (12.7 mm). The pin assignments and connector of the 16-bit ISA bus are shown in Fig. 1.12.

Rice. 1.12 - 16-bit ISA bus pinouts

Composition and purpose of bus linesISA

All ISA bus lines can be divided into six groups:

data lines;

address lines;

control lines;

direct memory access lines;

interrupt service lines;

power lines and auxiliary lines.

The designation and purpose of the lines is as follows.

1) AEN - Address Enable - used in DMA mode to inform all expansion cards that a DMA cycle is in progress. Installed and removed in parallel with the address.

2) BALE - Address Latch Enable Buffered. Address bits strobe signal. Setting the level high indicates the beginning of a bus cycle and the start of issuing a valid (but not yet established) address to the address lines. The falling edge of the signal indicates that the address is set and is used to store (“latched”) the state of the SAOO...SA19 and LA17...LA23 lines in the memory modules. Output stage type TTL.

3) I/O CH RDY (I/O Channel Ready - input/output channel readiness). This signal, usually high, is driven low by memory or an external device to prolong the access cycle. Any slow device using this signal must keep it low until it performs an address recognition operation and executes a read or write command. The communication cycle in response to the removal of the signal is extended by an integer number of clock cycles of the SYSCLK signal. The line should not be low for more than 15 µs and should be driven by an open collector device.

4) -DACK0...-DACK7. (DMA request ACKnowledge - DMA request confirmation). Direct access confirmation signal. The signal is generated by the DMA controller. Output stage type TTL.

5) DRQ0...DRQ7. (DMA ReQuest - DDP Request). Direct Memory Access Request Signals. The signal is generated by the I/O device. The request is perceived by the DMA controller and, in single exchanges, is reset with the arrival of the corresponding signal DACK i.

6) -I/O CH CK. (I/O Channel Check - Input/Output Error). The signal is generated by any executor - an input/output device or memory to inform the master about an error, for example about a parity error in a memory module. Output stage type - open collector.

7) -I/O CS16. (I/O Cycle Select 16 - Select a 16-bit cycle for an I/O device). The signal is generated by the I/O device to tell the master that it can handle 16-bit data. Output stage type - open collector.

8) -IOR. (I/O Read - Reading from an I/O device). Strobe signal for reading data from an input/output device. Output stage type - three states.

9) -IOW. (I/O Write - Writing to an I/O device). A strobe signal used to determine the moment in time when it is possible to begin recording data set by the master.

10) IRQ3...IRQ7, IRQ9...IRQ12, IRQ14, IRQ15. (Interrupt ReQuest - Interrupt request). The signal is generated by a device requesting a bus for exchange. Interrupt requests are sent to the input of the interrupt controller located on the system board. If the corresponding level is not blocked, then the rising edge of IRQ i causes an interruption of the processor and a transition to the service program for the corresponding request. A high level of IRQ i must be maintained until the interrupt confirmation signal from the central processor arrives at the interrupt controller.

11) LA17..LA23. (Latchable Address - Address that requires memorization in the executor). The signal can be generated by the CPU, the DMA controller, or the master on the expansion board. The signals are used to address high-speed memory modules on the bus, providing an address space expansion of up to 16 MB. Unlike signals SA0...SA19, whose steady-state values ​​are guaranteed throughout the entire bus cycle, signals LA17...LA23 are provided by the master only when the BALE signal level is high.

12) -MASTER. (Master - Master). The signal is generated by the master on the expansion board. With a low signal level, one of the expansion cards reports that it controls the bus - it is a master.

13) -MEM CS16. (MEMory 16-bit Chip Select - 16-bit memory). With a low signal level, the memory module being accessed informs the master that it can support 16-bit transfers with one wait state in the current exchange cycle.

14) -MEMR,SMEMR. (MEMory Read, System MEMory Ready - Reading from memory). The signals can be generated by the CPU or by a master on the expansion board. Signals are used to request that data be read from memory. Addresses in a zone up to 1 MB are accessed with active (low) SMEMR and MEMR signals, above 1 MB - with inactive (high) SMEMR and active (low) MEMR signals.

15) -MEMW, SMEMW. (MEMory Write, System MEMory Write - Writing to memory). The signal is generated by the CPU or a master on the expansion board. A low memory write signal indicates the start of a write cycle. Addresses in a zone up to 1 MB are accessed with active (low) -SMEMW and -MEMW, above 1 MB - with inactive (high) -SMEMW and active (low) -MEMW.

16)OSC. (OSCillator - Clock generator). The signal is generated by the central processing unit. Signal with a frequency of 14.31818 MHz and a duty cycle of 50%. In general, it is not synchronized with the processor clock speed.

17) -OWS. (0 Wait States - 0 wait cycles). The signal is set by the executor to inform the master about the need to carry out an exchange cycle without inserting a wait cycle, if the duration of the standard cycle is long for it. Generated after the BALE signal goes low. Must be synchronized with the SYSCLK signal. The output stage type is open collector.

18) -REFRESH. (REFRESH - Regeneration). The signal is generated by the regeneration controller to inform all devices connected to the backbone that the computer's dynamic RAM is being regenerated (every 15 μs).

19) RESET. (Reset - Reset). A reset signal, a high (active) level of which returns all devices to their original state. The signal is generated by the central processor when the power is turned on or off, as well as when the RESET button is pressed.

20) SA0...SA19. (System Address - System address bus). The signals are generated by the CPU, DMA controller or memory module. Serve to address I/O devices and memory. They are also called latched address bits because they are valid throughout the entire exchange cycle. They are used to transfer the least significant 20 bits of memory addresses (the address contains 24 bits in total).

21) -SBHE. (System Bus High Enable - Enable transmission of the high byte on the bus). The signal determines the type of data transfer cycle - 8 or 16 bit. Produced in parallel with signals SA0...SA19. The signal is generated by the CPU or memory module. A low signal level indicates the transmission of the high byte of data along lines SD8...SD15. Together with the SAO signal, it makes it possible to determine the type of bus cycle.

Table 1.1 – Determination of the type of data transmission cycle on the bus

22) SD0...SD7. (System Data - System data bus, low byte). The signal is generated by the CPU, memory module, master on the expansion board, and input/output device module. Transmission lines on the low data byte bus. 8-bit devices must use only these lines for data transfer. If software supports 16 or 32-bit transfers on an 8-bit data bus, the motherboard generates two or four consecutive transfer cycles on these lines.

23) SD8...SD15. System Data (System data bus, high byte). The signal is generated by the CPU, memory module, master on the expansion board, and input/output device module. The high byte of the system data bus is used for data transfer by 16-bit devices.

24) SYSCLK (System Clock, Bus Clock - bus clock signal). System clock signal with duty cycle 2 (square wave). In most computers, the signal is not synchronized to the CPU frequency, and its frequency is 8 MHz. Output stage type - three states.

25) TC. (Terminal Count - The count is completed). The signal is generated by the DMA controller and is used when completing block transfers. The signal reports the completion of the last cycle when transmitting a data array via the DMA channel.

Having analyzed the above signals, we can conclude what exchange operations on the ISA system bus are performed with devices

I/O In software and DMA modes, four types of operations (cycles) are performed on the ISA bus:

1 - write operation to memory;

2 - read operation from memory;

3 - write operation to an input/output device;

4 - read operation from an input/output device.

Electrical characteristics of the busISA

The ISA bus standard defines the input and output current requirements for the receivers and signal sources of each expansion card. The output stages of system airborne signal transmitters must produce a low-level current of at least 24 mA (this applies to all types of output stages), and a high-level current of at least 3 mA (for tri-state and TTL outputs).

System receiver input stages must consume no more than 0.8 mA of low-level input current and no more than 0.04 mA of high-level input current.

In addition, it is necessary to take into account that the maximum length of the printed conductor from the contact of the main connector to the pin of the microcircuit should not exceed 65 millimeters, and the maximum capacitance relative to ground for each contact of the main connector should not be more than 20 pF.

Load resistors are connected to some lines of the main line, going to the +5 V power bus. 4.7 kOhm resistors are connected to the lines -IOR, -IOW, -MEMR, -MEMW, -SMEMR, -SMEMW, -I/O CH SK, to to the -I/O CS 16, -MEM CS 16, -REFRESH, -MASTER, -OWS lines - 300 Ohms, and to the I/O CH RDY line - 1 kOhm. In addition, series resistors are connected to some lines of the trunk: 22 Ohm resistors are connected to the -IOR, -IOW, -MEMR, -MEMW, -SMEMR, -SMEMW and OSC lines, and 27 Ohm resistors are connected to the SYSCLK line.

Table 1.1 - Description of ISA bus signals

Designation	Purpose	Direction- tion	Source type
	Address signals
L.A.<23...17>	Address signals
	High byte resolution on SD lines<15...8>
	Strobe for writing addresses along LA lines
	Address resolution. Informs devices that DMA loops are running on the bus
	Data bus
	Read memory (read memory within the first megabyte of address space)
	Write to memory (write to memory within the first megabyte of address space)
	Reading UVV
	Recording in UVV
	Memory cycle selection, indicates that the memory is 16-bit
	Selecting a cycle for the airwave indicates that the airwave is 16-bit
	I/O channel readiness. Designed to extend access cycles
	0 wait cycles
	Memory regeneration
	Leading. Designed to capture the bus with an external board
	Checking the I/O channel. Fatal error message
	Resetting devices
	System frequency
	Frequency equal to 14.3818 MHz
IRQ<15,14,12, 11,10,9,7...3>	Interrupt Request
DRQ<7...5,3...0>	Request for RAP
DASK<7...5, 3...0>	RAP confirmation
	End of DAP count

Note:

The following notations are used in the table:

the “-” (minus) sign before the signal designation means that the active level of this signal is logical zero;

I – the signal is input for external boards;

O – the signal is output for external boards;

I/O – the signal is both input and output for external boards;

THREE – output of a microcircuit with three permissible output states;

TTL – output of transistor-transistor logic chip;

OK – open collector output.

Table 1.2 shows the electrical characteristics of the ISA bus signal sources.

Table 1.2 - Electrical characteristics of ISA bus signal sources

	transmitter	Receiver	transmitter	receiver		Transmitter

Notes:

all currents in the table are indicated in milliamps. The “-” sign in front of the current value means that the current flows from the external board into the bus slot;

a line with an open collector output can be connected to the TTL input;

along a line with an open collector output, the current Ioh (leakage current) should not exceed 0.4 milliamps for each slot.

1.2.2 Design features of system bus modules

When developing a module, it is necessary first of all to formulate the requirements for it and analyze the functions that the computer must perform using this module.

When designing, informational, electrical and structural compatibility is necessary. Structural compatibility comes down to exact compliance with all dimensions of the board, connectors and fasteners. Information compatibility presupposes the precise implementation of exchange protocols and the correct use of bus signals (see above for the main ISA bus signals). Electrical compatibility implies matching the levels of input, output and supply voltages and currents.

When designing airborne components included in the airborne interface part, it is necessary to take into account the timing diagrams of the ISA system bus (Figure 1.9). The most important time intervals when designing air-blasts are:

the delay between setting the address and the leading edge of the exchange strobe (at least 91 ns) - determines the time for recognition of its address by the designed airborne device;

exchange strobe duration (at least 176 ns);

the delay between the leading edge of the -IOR signal and the setting of the read data by the US (no more than 110 ns) - determines the requirements for the performance of the airborne data buffer;

the delay between the falling edge of the -IOW signal and the recording of recorded data (at least 30 ns) - determines the requirements for the speed of the airborne airborne nodes receiving data.

The generalized block diagram of the airborne interface part includes all the following nodes (Figure 1.13):

input buffers (optional);

bidirectional data buffer (in general should be divided into two for each byte);

output buffer of control signals;

address selector (AS);

internal gate driver (STR);

asynchronous exchange signal generator I/O CH RDY (DK).

Rice. 1.13 - Generalized block diagram of the airborne interface part

Electrical matching uses buffering of system signals to ensure the required input and output currents (ISA voltage levels - TTL). For buffering, microcircuits of mainline receivers, transmitters, transceivers, also called buffers or drivers.

Receivers of main signals must satisfy two main requirements: low input currents and high speed (they must be able to work within the time intervals of exchange cycles allotted to them). The requirements for receivers are met by the following series of microcircuits: KP1533 (SN74ALS), K555 (SN74LS) and KP1554 (74AC). The values ​​of logical zero input currents for them are 0.2 mA, 0.4 mA and 0.2 mA, respectively, and the values ​​of time delays do not exceed 15 ns, 20 ns and 10 ns, respectively. Requirements for transmitters: high output current and high speed. Often they must also have a switchable output (for example, for a data bus), that is, an open collector or tri-state output. This is due to the need for the airwave to transition to a passive state in the event of no access to it. Requirements for transceivers include requirements for receivers and transmitters, that is, low input current, high output current, high speed and mandatory shutdown of outputs. It should be noted that in the simplest case (when there are few discharges), transceivers can be built on receiver and transmitter microcircuits.

The requirements for address selectors are high performance (the address selector must have a delay of no more than the interval between setting the address and the start of the exchange strobe signal), the ability to change selectable addresses (especially important for I/O devices due to the small number of free addresses) and low hardware costs.

It must be taken into account that the main type of exchange via ISA is synchronous exchange, i.e. exchange at the pace of the master without taking into account the speed of the performer. However, asynchronous exchange is possible, in which the “slow” executor suspends the operation of the master while it executes the required command. In this case, it is necessary to set the I/O CH RDY signal, the removal of which (setting it to a logical zero state) indicates that the performer is not ready to end the exchange cycle.

A large number of modules contain buffer RAM, which is used for intermediate storage of data when transferred from a computer to an external device or vice versa. Buffer RAM is used in two cases: 1) with slow external devices:

a) if it is necessary to maintain a constant rate of data output (reception);

b) when transferring large amounts of data to free up the processor for other tasks.

2) if external devices are fast and the computer cannot provide the required speed for receiving/outputting information.

With parallel access to buffer RAM, each RAM cell has its own address in the computer's address space (the so-called shared memory). Any master processor, DMA controller, etc.) can communicate with buffer RAM as with system memory, using all means, all addressing methods, and line processing commands. A window is allocated in the ISA memory address space into which buffer RAM addresses are projected

With sequential access, all buffer RAM cells are mapped to one address in the computer's address space, i.e. When accessing the same address, the processor accesses different buffer RAM cells at different times.

The basis of any module is a programmable LSI. However, there are other ways to build communication interface adapters, for example, based on programmable logic circuits (FPGAs) or on simple microcircuits. However, the best solution is to use specialized, programmable LSIs, which house all the functional units of the module.

1.3 Module design stages

It is necessary to develop a programmable digital signal generator with 1 output, that is, a square pulse generator. The maximum frequency of the output signal is 2 MHz. Programmable parameters - frequency and duty cycle. Thus, the output information will be a sequence of rectangular pulses characterized by different frequencies and duty cycles. The exchange of information between the PC and an external device must be controlled by the software part of the module being developed.

Based on the general principles of developing electronic circuits and the design features of input/output devices for the ISA bus, we will divide the task into several stages:

synthesis of a generalized hardware module circuit;

selection of specialized LSI;

synthesis of the module block diagram;

selection of address space for I/O ports and interrupt numbers;

synthesis of the module circuit diagram;

development of the software part of the external device initialization module;

development of the software part of the external device control module;

1.4 Conclusions to Chapter 1

In this chapter, in addition to the ISA system bus, some methods of constructing digital signal generators were discussed. The main differences in all options, excluding hardware ones, are the duration and frequency of the output signals. Based on the task, the maximum output frequency of the generator should be 2 MHz, but not one of the considered options meets this requirement. In addition, the module being developed requires software modification of the output signal parameters. In the above circuits, the signal characteristics can be influenced by changing the resistance or capacitance, however, the software implementation of this approach is very difficult to implement, and, among other things, the costs will increase several times. Based on the above, the considered options for constructing digital signal generators cannot be used in this project. The way out of this situation will be to use a microcontroller in the module being developed, the selection of which will be made in the next chapter.

2 Development of the module diagram

2.1 General information

IBM PC computers provide the ability to connect additional devices directly to the system bus. To do this, special sockets (“slots”) are installed on the main computer board, into which additional cards can be inserted that perform functions not provided for by the original computer configuration. Currently, a large assortment of additional boards are produced that perform a wide variety of functions, including expanding the capabilities of communication between the computer and external devices. If necessary, such boards can be made independently. This course project is devoted to the development of one type of such boards.

General diagram of an IBM-compatible computer from the point of view of using the ISA bus (Fig. 2.1) with a programmable digital signal generator connected to it:

Rice. 2.1 – General diagram of an IBM-compatible computer from the point of view of using the ISA bus

Designations:

CPU - central processing unit

KRP – memory regeneration controller

KPR – interrupt controller

PB - byte permutator

SP – system memory

UVV – input/output device

The module being developed is structurally connected to the ISA bus as follows (Fig. 2.2):

Rice. 2.2 – Organization of the backplane bus

2.2 Development of a generalized module diagram

The module (Fig. 2.3) contains the following components:

Interface block for connecting to a computer (with ISA bus). Serves to connect the module to the bus. Used to transmit control signals and data between the bus and the module. Consists of an address selector and a data buffer between the VLSI and the ISA bus.

DTE – data terminal equipment. A digital signal programmed by the module is supplied to it.

Rice. 2.3 – Generalized diagram of the ISA bus module

The generalized circuit of a digital signal generator (Fig. 2.4) contains the following blocks:

address selector (SA)

specialized VLSI

bidirectional data buffer (DB)

Rice. 2.4 – Generalized circuit of a digital signal generator

The address selector analyzes the -AEN signal (whether a direct memory access cycle is running on the bus at this time) and the address set on the address bus (SA). If the call goes to the designed board, then the CA generates a strobe that allows the operation of the VLSI and the bidirectional buffer between the VLSI and the ISA bus. VLSI, using a read (-IOR) or write (-IOW) signal, reads or transmits data to the data bus (SD). The data sequence arrives at the data terminal equipment (DTE) as a digital signal.

2.3 Selection of VLSI and description of its structure

After analyzing the reference literature on various VLSIs, we can highlight the KR580VI53 microcircuit. This chip is a device that generates software-controlled time delays (timer). The conventional graphic designation (UGO) of the microcircuit is shown in Figure 2.2, the block diagram is shown in Figure 2.3.

Figure 2.2 – UGO KR580VI53

Figure 2.3 – Block diagram of KR580VI53

The purpose of the microcircuit pins is given in Table 2.1.

Table 2.1 – Pin assignment of the KR580VI53 microcircuit
	Designation	Output type	Functional assignment of pins
		Inputs/outputs	Data channel
	CLK0, CLK1, CLK2		Synchronization of channels 0-2
	OUT0, OUT1, OUT2		Signals of channels 0, 1, 2 respectively
	GATE1, GATE2, GATE3		Counter control inputs
			Channel selection signal 0, 1, 2
			Chip selection
			Supply voltage 5V±5%

The KR580VI53 microcircuit contains three independent identical channels: 0, 1, 2. Let's consider the purpose of the main components.

The channel selection circuit generates control signals for channels 0, 1, 2, internal and external data transmissions, and reception of control words.

The data channel buffer consists of eight bidirectional shapers with the output state “Off” and interfaces the timer with the MP data bus. Through the channel buffer, the control word is written to the mode registers and counting parameters to the counters of each channel. The circuits of channels 0, 1, 2 are identical and contain mode registers, control circuits, clock circuits and counters. The mode register is for recording information only. It receives and stores a control word, the code of which specifies the operating mode of the channel, determines the type of counting and the sequence of loading data into the counter. The channel control circuit synchronizes the operation of the counter in accordance with the programmed mode and the operation of the channel with the operation of the MP.

The channel synchronization circuit generates a series of internal clock pulses of a certain duration, which depends on the external clock frequency CLK and is determined by the internal timing circuits of the circuit. The maximum frequency of external synchronization signals CLK is no more than 2.6 MHz.

The channel counter is a 16-bit preset counter that operates on binary or BCD subtraction. The maximum number when counting is 2 16 when working in binary code or 10 4 when working in BCD. Channel counters are independent of each other and can have different operating modes and counting types. The counting in each channel is started, stopped and continued by the corresponding GATE “Channel Enable” signal.

Description of operating modes of VLSI KR580VI53

The microcircuit can operate in one of six main modes.

In mode 0 (interrupting terminal counting), a high-level voltage is generated at the channel output after counting the number loaded into the counter. The GATE signal provides the start of counting, its interruption (if necessary) and continuation of counting. Rebooting the counter during counting interrupts the current counting and resumes it according to the new program.

In mode 1 (operation of the waiting multivibrator), a negative pulse with a duration of
, (2.1)

where T CLK is the period of clock pulses;

n – number written into the counter.

The waiting multivibrator is triggered by the positive edge of the GATE signal. Each positive edge of this signal starts the current count or restarts the counter from the beginning. Resetting the counter during counting does not affect the current count.

In mode 2 (frequency generation), the timer functions as a divider of the input frequency CLK by n. In this case, the duration of the positive part of the period is equal to T CLK (n-1), and the negative part is T CLK. Rebooting during counting does not affect the current count.

Mode 3 (meander generation) is similar to mode 2, with the duration of the positive and negative half-cycles for an even number n equal to T CLK n/2. For an odd number n, the duration of the positive half-cycle is T CLK n/2, and the duration of the negative half-cycle is T CLK (n-1)/2.

In mode 4 (software formation of a single strobe), a pulse of negative polarity with a duration of
after counting the number loaded into the counter. Based on the GATE signal and after rebooting the counter, the operation of the channel in mode 4 is similar to mode 0.

In mode 5 (hardware generation of a single strobe), a pulse of negative polarity is generated at the channel output with a duration after the count of the number loaded into the counter.

2.4 Selecting the address space of I/O ports

When choosing the address zone of the module being designed, it is necessary to take into account the distribution of standard I/O addresses and select addresses from free zones. Table 2.5 shows a map of the UVB addresses of the IBM PC architecture.

Table 2.5 - IBM PC architecture UVB address map
Address zone	I/O device
	DMA controller (DMA master)
	Interrupt controller (Master)
	Hardware control registers. I/O ports
	Timer control registers
	Keyboard Interface Controller (8042)
	RTC ports and CMOS I/O ports
	DDP registers
	Interrupt controller (Slave)
	DMA controller (DMA – slave)
	Math coprocessor
	Hard drive controller
	Parallel port #2
	Graphics controller
	Serial port #2
	Network ports
	Parallel port #1
	Parallel Port and Monochrome Adapter
	EGA adapter
	CGA adapter
	Floppy drive controller
	Serial port #1

Despite the potential for addressing 16 address lines, most often only the 10 low-order lines of SAO...SA9 are used, since most previously developed expansion cards only use them, and therefore, except in special cases, there is no point in processing the high-order bits of SA10.. .SA15.

The low-order address bits from the bus (SA0 and SA1) must be connected to the VLSI address inputs (A0 and A1). Based on the VLSI specification and the task at hand, the designed module will occupy three addresses in the address space. Let's choose an address

372h (001101110010b)-

373h (001101110011b)-

375h (001101110101b)-

Addresses 372h and 373h are used to load the channel 0 counter and channel 1 counter, respectively, and address 375h is used to load the control word into the mode register.

2.5 Development of module interface elements

The simplest solution when constructing an address selector is to use only logical element microcircuits. The main advantage of this approach is high performance (latency does not exceed 30 ns). However, there are also disadvantages:

The need to design the circuit again for each new address.

Inability to change address.

Difficulty in organizing the selection of several addresses.

The assignment for the course project does not say anything about the choice of I/O addresses. This means that we will implement the simplest option in terms of time and material costs with fixed addresses, i.e. We build an address selector using logical elements.

The functional diagram of the address selector is shown in Figure 2.8.

Rice. 2.8 – Functional diagram of the address selector

We use the K555AP6 microcircuit as a data buffer between the VLSI and the data bus (Fig. 2.9, Table 2.6).

		Operation

Table 2.6 – Truth table K555AP6

Rice. 2.9 – UGO microcircuit K555AP6

2.6 Selection of element base and development of a circuit diagram

To build a circuit diagram, you need to select an element base. Analyzing the reference literature and taking into account the requirements for receivers and transmitters, we will select the following microcircuits:

inverters – KR1533LN1,

“AND-NOT” elements - KR1533LA2, KR1533LA3,

“OR-NOT” elements - KR1533LE1,

counter – KR555IE10,

buffer between VLSI and bus – K555AP5.

To interface the signals -IOR, SA0 and SA1 with VLSI, “I” elements - KR1533LI1 will be used.

The signal from the OUT0 output of the zero channel is connected to the synchronization input of channel 1 in order to change the duty cycle and frequency of the output signal of the module being developed. The CT2 counter divides the CLK signal frequency by 4 in hardware, thus ensuring the maximum output signal frequency specified in the task (2 MHz). By programmatically changing the counting coefficient of channel 0 (N1), we will achieve a change in the frequency of the output signal. By changing the counting coefficient of channel 1 (N2), we will provide a software change in the duty cycle of the output signal. Both channels operate in mode 2.

The developed circuit diagram is shown in TPZHA E3.

2.7 Conclusions to Chapter 2

In this chapter, a generalized module circuit was developed, a specialized VLSI was selected, and its structure and operating modes were examined. Board input addresses have been selected. Based on the results of the second chapter, a schematic diagram of the device was designed.

According to the concept, a board can be produced that is inserted into the ISA bus slot of a computer and, in a software-controlled exchange mode, generates digital signals of a given frequency and duty cycle.

3 Development of software modules

3.1 Development of a software initialization module

The module programming algorithm depends on the type of programmable VLSI used and the exchange mode between the VLSI and the computer processor via the ISA system bus.

Initialization of hardware modules is carried out in several stages. At the first stage, the VLSI module is initialized. At subsequent stages, the interrupt system or DMA is initialized, depending on the data exchange modes used between the module and the system processor.

In this case, a program-controlled exchange is carried out, i.e. Only VLSI needs to be initialized. Another feature is that there is no need to block the interrupt system due to the fact that the module does not have an interrupt exchange mode.

The VLSI initialization procedure consists of programming the operating mode; it is necessary to load the CW control word from the microprocessor. In this case, the corresponding signals must be set at the address inputs A0 and A1, as well as , . Their combinations are duplicated in table 3.1.

The operating mode of VLSI KR580VI53 channels is programmed using simple input/output operations (Table 3.1)

					VLSI→data channel (reading channel 0 counter)
					VLSI→data channel (reading channel 1 counter)
					VLSI→data channel (reading channel 2 counter)
					No operations. VLSI data channel in high resistance state
					Ban. VLSI data channel in high resistance state

Each of the three VLSI channels is individually programmed by writing a control word to the mode register and a programmed number of bytes to the counter. The control word format is presented in Table 3.2.

Table 3.2 – Control word format
Status word bit	Purpose
	Code: 0 – binary, 1 – decimal
	Operating mode: 000 – mode 0; 001 – mode 1; X10 – mode 2; X11 – mode 3; 100 – mode 4; 101 – mode 5.
	00 – “latching” operation; 01 – low byte only; 10 – high byte only; 11 – low byte, then high byte.
	Mode register selection: 00 – channel 0, 01 – channel 1,

To initialize the VLSI, you must first write the control word for channel 0 and load counter 0, then write the control word for channel 1 and load counter 1. The control word is written, in contrast to loading counters, at one address (375h).

Thus, we need to write the control word at address 375h: 00110100b, then at address 372h we need to enter the programmed number N1 (counting coefficient) into the counter of channel 0. After this, we write the control word (01110100b) again and load parameter N2 into the counter at address 373h. Elements of the program are presented in Appendix A.

3.2 Conclusions to Chapter 3

The control functions that the control module performs are included in the initialization software module.

In this chapter, programming of the selected LSI was reviewed, and the software part of the module was developed. Software-controlled data exchange with the developed device has been implemented. The user enters the frequency and duty cycle of the digital signal, the values ​​​​of which he wants to receive at the output of the device. The software module initializes the VLSI device in accordance with the entered values ​​and the circuit begins generating a digital signal.

Conclusion

As a result of the course project, a review of existing analogues of the designed device was carried out, and skills were acquired in designing hardware and software modules of the ISA system bus.

A programmable digital signal generator with the following characteristics has also been developed:

• maximum output frequency 2 MHz;

  the ability to programmatically change frequency and duty cycle;

  input addresses: 372h, 373h, 375h.

Software modules were also developed to ensure the operation of the board.

The design was based on the K580VI53 programmable timer chip, operating in frequency generation mode. To ensure a maximum output frequency of 2 MHz, the clock pulses of the SYSCLK signal of the ISA bus (8 MHz) are divided by 4. 2 numbers are loaded into channel 0 and channel 1 of the programmable timer. The frequency is affected by both loaded numbers (the 2 MHz frequency is divided by a certain factor). The duty cycle is affected by the number recorded in the counter of channel 1. Thus, by loading certain values ​​into the counters, we have the ability to programmatically change the shape of the digital signal.

Appendix A
(informative)

Bibliography

Tsilker B.Ya., Orlov S.A. Organization of computers and systems: Textbook for universities. – St. Petersburg: Peter, 2004. – 686 p.: ill.

Shabalin L.A. Development of hardware and software modules for the ISA bus: guidelines for completing course work. – VyatGU. 2000 – 35 p.

Blokhin S.M. ISA bus of the personal computer IBM PC/AT - M.: PC "Spline", 1992.

Shilo V.L. Popular digital microcircuits: Directory. – M.: Radio and Communications, 1987. – 352 p.: ill. – (Mass Radio Library. Issue 1111).

Bychkov E.A. Architecture and interfaces of personal computers. – M.: Center “SKS”, 1993.

Novikov Yu.V., Kalashnikov O.A., Gulyaev S.E. Development of interface devices for a personal computer such as IBM PC - M.: Ekom., 1997.

Zavadsky V.A. Computer electronics - K.: VEK, 1996.

L.A. Maltseva, E.M. Fromberg, V.S. Yampolsky Fundamentals of digital technology. – M.: Radio and Communications, 1986. 128s.

Microprocessors and microprocessor sets of integrated circuits: Directory. In 2 vols. / V. – B. B. Abraytis, N. N. Averyanov, A. I. Belous and others; Ed. V. A. Shakhnova. - M.: Radio and communications, 1988. - T.1. - 386 p.: ill.

Myachev A.A., Ivanov V.V. Interfaces of computer systems based on mini- and microcomputers / Ed. B.N. Naumova. - M.: Radio and communication, 1986.

Appendix B
(Required)

List of abbreviations

CPU - central processing unit

DMA – direct memory access controller

KRP – memory regeneration controller

KPR – interrupt controller

PB - byte permutator

PGDS – programmable digital signal generator

SP – system memory

UVV – input/output device

CA – address selector

DTE – data terminal equipment

DB – data buffer

VLSI – Very Large Scale Integrated Circuits

COMPUTER – electronic computer

PC – personal electronic computer

PT – programmable timer

MP – microprocessor

FPGA – programmable logic integrated circuit

DMA – direct memory access

RAM - random access memory

UGO – symbolic graphic designation

LSI – large integrated circuit

TTL – transistor-transistor logic

Appendix B
(Required)

Program listing

#include //standard I/O library

#include //there is a prototype of the outp() function

#define CWT0 0x52 //CWT0 – 00110100b control word for channel 0

#define CWT1 0x116 //CWT1 – 01110100b control word for channel1

#define portc 0x375 // address for entering the control word into the mode register

//prototype of the initialization function

void InitPit (int N1, int N2); // frequency, duty cycle

//Entering the required parameters (N1, N2)

//Initializing the counter:

void InitPit(int N1, int N2)

(unsigned char p1,p2,t1,t2;

p1=(N1<<8)>>8;

t1=(N2<<8)>>8;

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The ISA (Industrial Standard Architecture) bus was used in the first IBM PC, released in 1981, and in 1984 in an extended 16-bit version in the IBM PC/AT. The ISA bus is the fundamental basis of personal computer architecture; it was used until the late 1990s. It seems strange that a bus with such an “ancient” architecture was used in high-performance computers produced before the late 1990s, but this is due to its reliability, broad capabilities and compatibility. In addition, this bus still works faster than most peripheral devices connected to it.

Note!

The ISA bus is practically not found in modern desktop systems, and the number of companies producing ISA boards is extremely limited. ISA boards are still popular in industrial systems(PICMG), but in the near future they will disappear there too.

There are two versions of the ISA bus, differing in the number of data bits: the old 8-bit version and the new 16-bit version. The old version ran at a clock frequency of 4.77 MHz in PC and XT class computers. The new version was used in AT class computers with clock frequencies of 6 and 8 MHz. Later, agreement was reached on a standard maximum clock speed of 8.33 MHz for both versions of the buses, ensuring their compatibility. Some systems allow the use of buses when operating at higher frequencies, but not all adapter cards can handle this speed. It takes two to eight clock cycles to transmit data on the bus. Therefore, the maximum data transfer rate on the ISA bus is 8.33 MB/s:

8.33 MHz × 16 bits: 2 clocks = 66.64 Mbps (or 8.33 MB/s)

The 8-bit bus has half the bandwidth (4.17 MB/s). However, do not forget that these are theoretical maximums - due to the complex data exchange protocol, the real throughput tires are much lower (usually half). Even so, the ISA bus is faster than most peripherals connected to it.

8-bit ISA bus

This bus was used in the first IBM PC. It is not used in new systems, but hundreds of thousands of computers with this bus are still in use, including systems based on 286 and 386 processors.

An adapter board with 62 pins is inserted into the connector. The connector supplies 8 data lines and 20 address lines, which allows you to address up to 1 MB of memory. The purpose and pin locations of the 8-bit ISA bus connector are shown in the figure.

Although this bus is very simple, IBM did not publish a complete description of it and timing diagrams for the signals on the data and address lines until 1987. Therefore, when creating adapter boards for the first IBM-compatible computers, developers had to understand its operation themselves. As IBM-compatible computers became more common and became an industry standard, the development process became much easier.

The 8-bit ISA bus adapter board has the following dimensions:

• height - 4.2 inches (106.68 mm);

16-bit ISA bus

IBM literally blew up the PC world with the introduction of the AT model in 1984, equipped with a 286 processor. This processor supported a 16-bit data bus, which allowed for interaction between the processor, system board and memory using 16-bit rather than 8-bit data. Although the processor could be installed on a motherboard with an 8-bit I/O bus, it still provided increased performance when exchanging data with various boards connected to the bus.

Instead of creating a new I/O bus, IBM decided to make the system compatible with 8- and 16-bit adapters by keeping the same 8-bit connector but adding an additional one to it. The result was a connector for installing 16-bit adapters. First introduced in PC/AT computers in August 1984, the 16-bit ISA bus was also called the AT bus.

An additional connector in each 16-bit expansion slot adds 36 pins (the total number of data pins increases to 98) needed to transfer higher-bit data. In addition, the assignment of two pins of the 8-bit part of the connector has been changed. However, such changes did not in any way affect the performance of 8-bit boards.

A typical Class AT adapter board has the following dimensions:

• height - 4.8 inches (121.92 mm);
• length - 13.13 inches (333.5 mm);
• thickness - 0.5 inches (12.7 mm).

In AT-class computers, boards with a height of both 4.8 inches and 4.2 inches (corresponding to older boards for PC/XT class computers) can be found. The reduced-height boards were installed in the XT-class computer model 286. This model, with a motherboard designed for an AT-class computer, used an XT case, so the height of the adapter cards had to be reduced to 4.2 inches. After this, most manufacturers began to produce only adapters with a reduced height that can be installed in any case.

32-bit ISA bus

Some time after the release of the 32-bit processor, the first standards for the corresponding bus were developed. Even before the first designs of the MCA and EISA architectures appeared, some companies began to develop their own designs that were extensions of the ISA architecture. Although relatively few were produced, some of them are still found today.

Additional lines of these buses were usually used only when working with memory expansion cards and video adapters produced by the companies that created this standard. Their parameters and connector layouts differ significantly from the standard ones; moreover, their specifications and contact diagrams were not distributed.