Switch power supply 200w power supply for a screwdriver. Scheme

Here is a complete description of the circuit diagram for one of the 200-watt switching power supplies (PS6220C, made in Taiwan).

AC mains voltage is supplied via the mains switch PWR SW via mains fuse F101 4A, noise suppression filters formed by elements C101, R101, L101, C104, C103, C102 and chokes L102, L103 on:

• a three-pin output connector to which the display power cable can be connected;
• two-pin connector JP1, the mating part of which is located on the board.

From connector JP1, alternating mains voltage is supplied to:

• bridge rectification circuit BR1 through thermistor THR1;
• the primary winding of the starting transformer T1.

At the output of rectifier BR1, smoothing filter capacitances C1, C2 are included. The THR thermistor limits the initial surge of charging current for these capacitors. 115V/230V SW switch allows UPS power supply both from a 220-240 V network and from a 110/127 V network.

High-ohm resistors R1, R2, shunt capacitors C1, C2 are baluns (equalize the voltages on C1 and C2), and also ensure the discharge of these capacitors after the UPS is turned off from the network. The result of the operation of the input circuits is the appearance on the rectified mains voltage bus of a direct voltage Uep equal to +310 V, with some ripples. This UPS uses a starting circuit with forced (external) excitation, which is implemented on a special starting transformer T1, on the secondary winding of which, after the UPS is connected to the network, an alternating voltage with the frequency of the supply network appears. This voltage is rectified by diodes D25, D26, which form a full-wave rectification circuit with a midpoint with the secondary winding T1. C30 is a smoothing filter capacitance, which generates a constant voltage used to power the control chip U4.

The TL494 IC is traditionally used as a control chip in this UPS.

The supply voltage from capacitor C30 is supplied to pin 12 of U4. As a result, the output voltage of the internal reference source Uref = -5 V appears at pin 14 of U4, the internal sawtooth voltage generator of the microcircuit starts, and control voltages appear at pins 8 and 11, which are sequences of rectangular pulses with negative leading edges, shifted relative to each other for half the period. Elements C29, R50 connected to pins 5 and 6 of the U4 microcircuit determine the frequency of the sawtooth voltage generated by the internal generator of the microcircuit.

The matching stage in this UPS is made according to a transistorless circuit with separate control. The supply voltage from capacitor C30 is supplied to the middle points of the primary windings of control transformers T2, T3. The output transistors of IC U4 perform the functions of matching stage transistors and are connected according to the circuit with the OE. The emitters of both transistors (pins 9 and 10 of the microcircuit) are connected to the “case”. The collector loads of these transistors are the primary half-windings of the control transformers T2, T3, connected to pins 8, 11 of the U4 microcircuit (open collectors of the output transistors). The other halves of the primary windings T2, T3 with diodes D22, D23 connected to them form demagnetization circuits for the cores of these transformers.

Transformers T2, T3 control powerful transistors of the half-bridge inverter.

Switching the output transistors of the microcircuit causes the appearance of pulsed control EMF on the secondary windings of control transformers T2, T3. Under the influence of these EMFs, power transistors Q1, Q2 alternately open with adjustable pauses (“dead zones”). Therefore, through the primary winding of the power pulse transformer T5 flows alternating current in the form of sawtooth current pulses. This is explained by the fact that the primary winding T5 is included in the diagonal of the electrical bridge, one arm of which is formed by transistors Q1, Q2, and the other by capacitors C1, C2. Therefore, when any of the transistors Q1, Q2 is opened, the primary winding T5 is connected to one of the capacitors C1 or C2, which causes current to flow through it as long as the transistor is open.

Damper diodes D1, D2 ensure the return of energy stored in the leakage inductance of the primary winding T5 during the closed state of transistors Q1, Q2 back to the source (recuperation).

Capacitor C3, connected in series with the primary winding T5, eliminates the DC component of the current through the primary winding T5, thereby eliminating unwanted magnetization of its core.

Resistors R3, R4 and R5, R6 form basic dividers for powerful transistors Q1, Q2, respectively, and provide the optimal switching mode from the point of view of dynamic power losses on these transistors.

The flow of alternating current through the primary winding T5 causes the presence of alternating rectangular pulse EMF on the secondary windings of this transformer.

The T5 power transformer has three secondary windings, each of which has a terminal from the middle point.

Winding IV provides an output voltage of +5 V. The diode assembly SD2 (half bridge) forms a full-wave rectification circuit with a midpoint with winding IV (the midpoint of winding IV is grounded).

The diodes of the SD2 assembly are diodes with a Schottky barrier, which achieves the required speed and increases the efficiency of the rectifier.

Winding III together with winding IV provides an output voltage of +12 V together with the diode assembly (half bridge) SD1. This assembly forms, with winding III, a full-wave rectification circuit with a midpoint. However, the middle point of winding III is not grounded, but is connected to the +5 V output voltage bus. This will make it possible to use Schottky diodes in the +12 V generation channel, because the reverse voltage applied to the rectifier diodes with this connection is reduced to the permissible level for Schottky diodes.

Elements L1, C6, C7 form a smoothing filter in the +12 V channel.

Resistors R9, R12 are designed to accelerate the discharge of the output capacitors of the +5 V and +12 V buses after turning off the UPS from the network.

Winding II with five taps provides negative output voltages of -5 V and -12 V.

Two discrete diodes D3, D4 form a half-bridge of full-wave rectification in the -12 V generation channel, and diodes D5, D6 - in the -5 V channel.

Elements L3, C14 and L2, C12 form anti-aliasing filters for these channels.

Winding II, as well as winding III, is shunted by an RC damping circuit R13, C13.

The middle point of winding II is grounded.

Stabilization of output voltages is carried out different ways in different channels.

Negative output voltages -5 V and -12 V are stabilized using linear integrated three-terminal stabilizers U4 (type 7905) and U2 (type 7912).

To do this, the output voltages of the rectifiers from capacitors C14, C15 are supplied to the inputs of these stabilizers. The output capacitors C16, C17 produce stabilized output voltages of -12 V and -5 V.

Diodes D7, D9 ensure the discharge of output capacitors C16, C17 through resistors R14, R15 after turning off the UPS from the network. Otherwise, these capacitors would be discharged through the stabilizer circuit, which is undesirable.

Through resistors R14, R15, capacitors C14, C15 are also discharged.

Diodes D5, D10 perform a protective function in the event of breakdown of the rectifier diodes.

If at least one of these diodes (D3, D4, D5 or D6) turns out to be “broken”, then in the absence of diodes D5, D10 a positive pulse voltage would be applied to the input of the integrated stabilizer U1 (or U2), and through electrolytic capacitors Alternating current would flow through C14 or C15, which would lead to their failure.

The presence of diodes D5, D10 in this case eliminates the possibility of such a situation occurring, because the current closes through them.

For example, if diode D3 is “broken”, the positive part of the period when D3 should be closed, the current will be closed in the circuit: to D3 - L3 D7-D5 - “case”.

Stabilization of the +5 V output voltage is carried out using the PWM method. To do this, a measuring resistive divider R51, R52 is connected to the +5 V output voltage bus. A signal proportional to the output voltage level in the +5 V channel is removed from resistor R51 and fed to the inverting input of the error amplifier DA3 (pin 1 of the control chip). The direct input of this amplifier (pin 2) is supplied with a reference voltage level taken from resistor R48, which is included in the divider VR1, R49, R48, which is connected to the output of the internal reference source of the microcircuit U4 Uref = +5 V. When the voltage level on the + bus changes 5 V, under the influence of various destabilizing factors, the magnitude of the mismatch (error) between the reference and controlled voltage levels at the inputs of the error amplifier DA3 changes. As a result, the width (duration) of control pulses at pins 8 and 11 of the U4 microcircuit changes in such a way as to return the deviated output voltage +5 V to the nominal value (as the voltage on the +5 V bus decreases, the width of the control pulses increases, and as this voltage increases, decreases).

The +12 V output voltage in this UPS is not stabilized.

The level of output voltages in this UPS is adjusted only for the +5 V and +12 V channels. This adjustment is carried out by changing the level of the reference voltage at the direct input of the error amplifier DA3 using trimming resistor VR1.

When changing the position of the VR1 slider during the UPS setup process, the voltage level on the +5 V bus will change within certain limits, and therefore on the +12 V bus, because voltage from the +5 V bus is supplied to the middle point of winding III.

The combined protection of this UPS includes:

• a limiting circuit for controlling the width of control pulses;
• incomplete output overvoltage control circuit (only on the +5 V bus).

Let's look at each of these schemes.

The limiting control circuit uses current transformer T4 as a sensor, the primary winding of which is connected in series with the primary winding of the power pulse transformer T5.

Resistor R42 is the load of the secondary winding T4, and diodes D20, D21 form a full-wave alternating rectification circuit impulse voltage, removed from the load R42.

Resistors R59, R51 form a divider. Part of the voltage is smoothed out by capacitor C25. The voltage level on this capacitor depends proportionally on the width of the control pulses at the bases power transistors Q1, Q2. This level is fed through resistor R44 to the inverting input of the error amplifier DA4 (pin 15 of the U4 chip). The direct input of this amplifier (pin 16) is grounded. Diodes D20, D21 are connected so that capacitor C25, when current flows through these diodes, is charged to a negative (relative to the common wire) voltage.

In normal operation, when the width of the control pulses does not exceed acceptable limits, the potential of pin 15 is positive, due to the connection of this pin through resistor R45 to the Uref bus. If the width of the control pulses increases excessively for any reason, the negative voltage on capacitor C25 increases and the potential of pin 15 becomes negative. This leads to the appearance of the output voltage of the error amplifier DA4, which was previously equal to 0 V. A further increase in the width of the control pulses leads to the fact that the switching control of the PWM comparator DA2 is transferred to the amplifier DA4, and the subsequent increase in the width of the control pulses no longer occurs (limitation mode), because the width of these pulses no longer depends on the level of the feedback signal at the direct input of the error amplifier DA3.

The short circuit protection circuit in loads can be conditionally divided into protection of channels for generating positive voltages and protection of channels for generating negative voltages, which are implemented in approximately the same circuitry.

The sensor of the short-circuit protection circuit in the loads of channels generating positive voltages (+5 V and +12 V) is a diode-resistive divider D11, R17, connected between the output buses of these channels. The voltage level at the anode of diode D11 is a controlled signal. In normal operation, when the voltages on the output buses of the +5 V and +12 V channels are at nominal values, the anode potential of diode D11 is about +5.8 V, because current flows through the sensor divider from the +12 V bus to the +5 V bus along the circuit: +12 V bus - R17-D11 - +5 V bus.

The controlled signal from the anode D11 is fed to the resistive divider R18, R19. Part of this voltage is removed from resistor R19 and supplied to the direct input of comparator 1 of the U3 microcircuit of the LM339N type. The inverting input of this comparator is supplied with a reference voltage level from resistor R27 of the divider R26, R27 connected to the output of the reference source Uref=+5 V of the control chip U4. The reference level is selected such that, during normal operation, the potential of the direct input of comparator 1 would exceed the potential of the inverse input. Then the output transistor of comparator 1 is closed, and the UPS circuit operates normally in PWM mode.

In the case of a short circuit in the load of the +12 V channel, for example, the anode potential of diode D11 becomes equal to O V, so the potential of the inverting input of comparator 1 will become higher than the potential of the direct input, and the output transistor of the comparator will open. This will cause the closing of transistor Q4, which is normally open by the base current flowing through the circuit: Upom bus - R39 - R36 b-e Q4 - "case".

Turning on the output transistor of comparator 1 connects resistor R39 to the "case" and therefore transistor Q4 is passively turned off by zero bias. Closing transistor Q4 entails charging capacitor C22, which serves as a delay element for the protection. The delay is necessary for the reasons that during the process of the UPS entering mode, the output voltages on the +5 V and +12 V buses do not appear immediately, but as the high-capacity output capacitors are charged. The reference voltage from the source Uref, on the contrary, appears almost immediately after the UPS is connected to the network. Therefore, in the starting mode, comparator 1 switches, its output transistor opens, and if the delay capacitor C22 were missing, this would lead to the protection triggering immediately when the UPS is turned on to the network. However, C22 is included in the circuit, and the protection operates only after the voltage on it reaches the level determined by the values ​​of resistors R37, R58 of the divider connected to the Upom bus and which is the base for transistor Q5. When this happens, transistor Q5 opens, and resistor R30 is connected through the low internal resistance of this transistor to the “case”. Therefore, a path appears for the base current of transistor Q6 to flow through the circuit: Uref - unit Q6 - R30 - unit Q5 "case".

Transistor Q6 is opened by this current until saturation, as a result of which the voltage Uref = 5 V, which powers transistor Q6 along the emitter, is applied through its low internal resistance to pin 4 of the control chip U4. This, as was shown earlier, leads to the stop of the digital path of the microcircuit, the disappearance of output control pulses and the cessation of switching of power transistors Q1, Q2, i.e. to protective shutdown. A short circuit in the +5 V channel load will result in the anode potential of diode D11 being only about +0.8 V. Therefore, the output transistor of the comparator (1) will be open, and a protective shutdown will occur.

In a similar way, short-circuit protection is built in the loads of channels generating negative voltages (-5 V and -12 V) on comparator 2 of the U3 chip. Elements D12, R20 form a diode-resistive divider-sensor, connected between the output buses of the negative voltage generation channels. The controlled signal is the cathode potential of diode D12. During a short circuit in a -5 V or -12 V channel load, the potential of cathode D12 increases (from -5.8 to 0 V for a short circuit in a -12 V channel load and to -0.8 V for a short circuit in a -5 V channel load) . In any of these cases, the normally closed output transistor of comparator 2 opens, which causes the protection to operate according to the above mechanism. In this case, the reference level from resistor R27 is supplied to the direct input of comparator 2, and the potential of the inverting input is determined by the values ​​of resistors R22, R21. These resistors form a bipolarly powered divider (resistor R22 is connected to the bus Uref = +5 V, and resistor R21 is connected to the cathode of diode D12, the potential of which in normal operation of the UPS, as already noted, is -5.8 V). Therefore, the potential of the inverting input of comparator 2 in normal operation is maintained lower than the potential of the direct input, and the output transistor of the comparator will be closed.

Protection against output overvoltage on the +5 V bus is implemented on elements ZD1, D19, R38, C23. Zener diode ZD1 (with a breakdown voltage of 5.1 V) is connected to the +5 V output voltage bus. Therefore, as long as the voltage on this bus does not exceed +5.1 V, the zener diode is closed, and transistor Q5 is also closed. If the voltage on the +5 V bus increases above +5.1 V, the zener diode “breaks through”, and an unlocking current flows into the base of transistor Q5, which leads to the opening of transistor Q6 and the appearance of voltage Uref = +5 V at pin 4 of the control chip U4, those. to protective shutdown. Resistor R38 is a ballast for the zener diode ZD1. Capacitor C23 prevents the protection from triggering during random short-term voltage surges on the +5 V bus (for example, as a result of the voltage settling after a sudden decrease in the load current). Diode D19 is a decoupling diode.

The PG signal generation circuit in this UPS is dual-functional and is assembled on comparators (3) and (4) of the U3 microcircuit and transistor Q3.

The circuit is built on the principle of monitoring the presence of alternating low-frequency voltage on the secondary winding of the starting transformer T1, which acts on this winding only if there is a supply voltage on the primary winding T1, i.e. while the UPS is connected to the mains.

Almost immediately after the UPS is turned on, the auxiliary voltage Upom appears on capacitor C30, which powers the control chip U4 and the auxiliary chip U3. In addition, the alternating voltage from the secondary winding of the starting transformer T1 through diode D13 and current-limiting resistor R23 charges capacitor C19. The voltage from C19 powers the resistive divider R24, R25. From resistor R25, part of this voltage is supplied to the direct input of comparator 3, which leads to the closing of its output transistor. The output voltage of the internal reference source of the microcircuit U4 Uref = +5 V, which appears immediately after this, powers the divider R26, R27. Therefore, the reference level from resistor R27 is supplied to the inverting input of comparator 3. However, this level is chosen to be lower than the level at the direct input, and therefore the output transistor of comparator 3 remains in the off state. Therefore, the process of charging the holding capacity C20 begins along the chain: Upom - R39 - R30 - C20 - “housing”.

The voltage, which increases as capacitor C20 charges, is supplied to the inverse input 4 of the U3 microcircuit. The direct input of this comparator is supplied with voltage from resistor R32 of the divider R31, R32 connected to the Upom bus. As long as the voltage across the charging capacitor C20 does not exceed the voltage across resistor R32, the output transistor of comparator 4 is closed. Therefore, an opening current flows into the base of transistor Q3 through the circuit: Upom - R33 - R34 - b-e Q3 - “case”.

Transistor Q3 is open to saturation, and the PG signal taken from its collector has a passive low level and prevents the processor from starting. During this time, during which the voltage level on capacitor C20 reaches the level on resistor R32, the UPS manages to reliably enter the rated operating mode, i.e. all its output voltages appear in full.

As soon as the voltage on C20 exceeds the voltage removed from R32, comparator 4 will switch and its output transistor will open. This will cause transistor Q3 to close, and the PG signal taken from its collector load R35 becomes active (H-level) and allows the processor to start.

When the UPS is turned off from the network, the alternating voltage disappears on the secondary winding of the starting transformer T1. Therefore, the voltage on capacitor C19 quickly decreases due to the low capacitance of the latter (1 μF).

As soon as the voltage drop across resistor R25 becomes less than that across resistor R27, comparator 3 will switch and its output transistor will open. This will entail a protective shutdown of the output voltages of the control chip U4, because transistor Q4 will open. In addition, through the open output transistor of comparator 3, the process of accelerated discharge of capacitor C20 will begin along the circuit: (+)C20 - R61 - D14 - k-e day off comparator transistor 3 - “case”. As soon as the voltage level at C20 becomes less than the voltage level at R32, comparator 4 will switch and its output transistor will close. This will cause transistor Q3 to open and the PG signal to go to an inactive low level before the voltages on the UPS output buses begin to decrease unacceptably. This will trigger the computer's system reset signal and original state the entire digital part of the computer.

Both comparators 3 and 4 of the PG signal generation circuit are covered by positive feedback using resistors R28 and R60, respectively, which speeds up their switching.

A smooth transition to mode in this UPS is traditionally ensured using the forming chain C24, R41, connected to pin 4 of the control chip U4. The residual voltage at pin 4, which determines the maximum possible duration of the output pulses, is set by the divider R49, R41.

The fan motor is powered by voltage from capacitor C14 in the -12 V voltage generation channel through an additional decoupling L-shaped filter R16, C15.