What is a pci e slot? SSD with PCI Express interface: review and testing of five models. PCI Express slots

If you ask which interface should be used for a solid-state drive that supports the NVMe protocol, then any person (who even knows what NVMe is) will answer: of course PCIe 3.0 x4! True, he will most likely have difficulties with justification. At best, we will get the answer that such drives support PCIe 3.0 x4, and interface bandwidth matters. It is, but all the talk about it began only when some drives in some operations became cramped within the framework of “regular” SATA. But between its 600 MB/s and the (equally theoretical) 4 GB/s of the PCIe 3.0 x4 interface there is simply an abyss, filled with a ton of options! What if one PCIe 3.0 line is enough, since this is already one and a half times larger than SATA600? Adding fuel to the fire are controller manufacturers who are threatening to switch to PCIe 3.0 x2 in budget products, as well as the fact that many users do not have such and such. More precisely, theoretically there are, but they can be released only by reconfiguring the system or even changing something in it that you don’t want to do. But I want to buy a top-end solid-state drive, but there are fears that there will be no benefit at all from this (even moral satisfaction from the results of test utilities).

But is this true or not? In other words, is it really necessary to focus exclusively on the supported operating mode - or is it still possible in practice? give up principles? This is exactly what we decided to check today. Let the check be quick and not pretend to be exhaustive, but the information received should be enough (as it seems to us) at least to think about it... For now, let's briefly get acquainted with the theory.

PCI Express: existing standards and their bandwidth

Let's start with what PCIe is and at what speed this interface operates. It is often called a “bus,” which is somewhat ideologically incorrect: as such, there is no bus to which all devices are connected. In reality there is a set of point-to-point connections (similar to many other serial interfaces) with a controller in the middle and devices attached to it (each of which in itself can be a hub of the next level).

First version PCI Express appeared almost 15 years ago. The focus on use inside a computer (often within the same board) made it possible to make the standard high-speed: 2.5 gigatransactions per second. Because the interface is serial and full-duplex, a single PCIe lane (x1; effectively an atomic unit) provides data transfer speeds of up to 5 Gbps. However, in each direction it is only half of this, i.e. 2.5 Gbps, and this is the full speed of the interface, not the “useful” one: to improve reliability, each byte is encoded with 10 bits, so the theoretical throughput of one PCIe lane 1.x is approximately 250 MB/s each way. In practice, it is still necessary to transfer service information, and in the end it is more correct to talk about ≈200 MB/s of user data transfer. Which, however, at that time not only covered the needs of most devices, but also provided a solid reserve: just remember that the predecessor of PCIe in the segment of mass system interfaces, namely the PCI bus, provided a throughput of 133 MB/s. And even if we consider not only mass implementation, but also all PCI options, the maximum was 533 MB/s, and for the entire bus, i.e., such a PS was divided into all devices connected to it. Here, 250 MB/s (since for PCI, too, the total and not the useful throughput is usually given) per line - in exclusive use. And for devices that need more, it was initially possible to aggregate several lines into a single interface, in powers of two - from 2 to 32, i.e., the x32 version provided for by the standard could transmit up to 8 GB/s in each direction. In personal computers, x32 was not used due to the complexity of creating and wiring the corresponding controllers and devices, so the maximum option was 16 lines. It was (and is still used) mainly by video cards, since most devices do not require so much. In general, for a considerable number of them, one line is enough, but some successfully use both x4 and x8: just on the storage topic - RAID controllers or SSDs.

Time did not stand still, and about 10 years ago the second version of PCIe appeared. The improvements were not only about speeds, but a step forward was also taken in this regard - the interface began to provide 5 gigatransactions per second while maintaining the same encoding scheme, i.e., the throughput was doubled. And it doubled again in 2010: PCIe 3.0 provides 8 (rather than 10) gigatransactions per second, but the redundancy has been reduced - now 130 bits are used to encode 128, not 160 as before. In principle, the PCIe 4.0 version with another doubling of speeds is already ready to appear on paper, but we are unlikely to see it in hardware in the near future. In fact, PCIe 3.0 is still used in many platforms in conjunction with PCIe 2.0, because the performance of the latter is simply... not needed for many applications. And where needed, the good old method of line aggregation works. Only each of them has become four times faster over the past years, i.e. PCIe 3.0 x4 is PCIe 1.0 x16, the fastest slot in computers of the mid-2000s. This option is supported by top-end SSD controllers, and it is recommended to use it. It is clear that if such an opportunity exists, a lot is not a little. What if she doesn't exist? Will there be any problems, and if so, what are they? This is the question we have to deal with.

Testing methodology

It is not difficult to carry out tests with different versions of the PCIe standard: almost all controllers allow you to use not only the one they support, but also all earlier ones. It’s more difficult with the number of lanes: we wanted to directly test options with one or two PCIe lanes. The Asus H97-Pro Gamer board we usually use is Intel chipset The H97 does not support the full set, but in addition to the x16 “processor” slot (which is usually used), it has another one that operates in PCIe 2.0 x2 or x4 modes. We used this trio, adding to it the PCIe 2.0 “processor” slot mode in order to evaluate whether there was a difference. Still, in this case, there are no extraneous “intermediaries” between the processor and the SSD, but when working with a “chipset” slot, there is: the chipset itself, which is actually connected to the processor by the same PCIe 2.0 x4. It was possible to add several more operating modes, but we were still going to conduct the main part of the study on another system.

The fact is that we decided to take this opportunity and at the same time check one “urban legend”, namely the belief about the usefulness of using top processors for testing drives. So we took the eight-core Core i7-5960X - a relative of the Core i3-4170 usually used in tests (these are Haswell and Haswell-E), but which has four times more cores. In addition, the Asus Sabertooth X99 board found in the bins is useful to us today due to the presence of a PCIe x4 slot, which in fact can work as x1 or x2. In this system, we tested three x4 options (PCIe 1.0/2.0/3.0) from the processor and chipset PCIe 1.0 x1, PCIe 1.0 x2, PCIe 2.0 x1 and PCIe 2.0 x2 (in all cases, chipset configurations are marked in the diagrams with (c)). Does it make sense to turn to the first version of PCIe now, given the fact that there is hardly a single board that supports only this version of the standard and can boot from an NVMe device? From a practical point of view, no, but to check the a priori assumed ratio of PCIe 1.1 x4 = PCIe 2.0 x2 and the like, it will be useful to us. If the test shows that the bus scalability corresponds to the theory, then it doesn’t matter that we have not yet been able to obtain practically significant ways to connect PCIe 3.0 x1/x2: the first will be identical to PCIe 1.1 x4 or PCIe 2.0 x2, and the second - PCIe 2.0 x4 . And we have them.

In terms of software, we limited ourselves to only Anvil’s Storage Utilities 1.1.0: it measures a variety of low-level characteristics of drives quite well, and we don’t need anything else. Quite the contrary: any influence of other components of the system is extremely undesirable, so low-level synthetics for our purposes have no alternative.

We used a 240 GB Patriot Hellfire as a “working fluid”. As it was established during testing, this is not a performance record-holder, but its speed characteristics are quite consistent with the results of the best SSDs of the same class and the same capacity. Yes, and there are already slower devices on the market, and there will be more and more of them. In principle, it would be possible to repeat the tests with something faster, but, in our opinion, there is no need for this - the results are predictable. But let’s not get ahead of ourselves, but let’s see what we got.

Test results

When testing Hellfire, we noticed that the maximum speed for sequential operations can be “squeezed out” of it only with a multi-threaded load, so this also needs to be taken into account for the future: the theoretical throughput is only theoretical, because the “real” data received in different programs according to different scenarios, they will no longer depend on it, but on these very programs and scenarios - in the case, of course, when force majeure circumstances do not interfere :) We are now observing exactly such circumstances: it was already said above that PCIe 1 .x x1 is ≈200 MB/s, and that's what we see. Two PCIe 1.x lanes or one PCIe 2.0 lanes are twice as fast, and that's exactly what we're seeing. Four PCIe 1.x lanes, two PCIe 2.0 or one PCIe 3.0 are even twice as fast, which was confirmed for the first two options, so the third is unlikely to be different. That is, in principle, scalability, as expected, is ideal: the operations are linear, flash handles them well, so the interface matters. Flash stops cope well to PCIe 2.0 x4 for recording (which means PCIe 3.0 x2 is also suitable). Reading “may” be more, but the last step already gives one and a half, and not twofold (as it potentially should be) increase. We also note that there is no noticeable difference between the chipset and processor controllers, and between platforms as well. However, LGA2011-3 is a little ahead, but only slightly.

Everything is smooth and beautiful. But does not tear templates: the maximum in these tests is only slightly more than 500 MB/s, and this is quite capable even of SATA600 or (in the application to today's testing) PCIe 1.0 x4 / PCIe 2.0 x2 / PCIe 3.0 x1. That’s right: don’t be alarmed by the release of budget controllers for PCIe x2 or the presence of only so many lines (and the 2.0 version of the standard) in the M.2 slots on some boards when more is not needed. Sometimes you don’t need that much: the maximum results were achieved with a queue of 16 commands, which is not typical for mass-produced software. More often there is a queue with 1-4 commands, and for this you can get by with one line of the very first PCIe and even the very first SATA. However, there are overheads and other things, so a fast interface is useful. However, being too fast is perhaps not harmful.

Also, in this test the platforms behave differently, and with a single command queue - fundamentally differently. The “trouble” is not that many cores are bad. They are not used here anyway, except perhaps one, and not so much that the boost mode is fully deployed. So we have a difference of about 20% in core frequency and one and a half times in cache memory - in Haswell-E it operates at a lower frequency, and not synchronously with the cores. In general, a top-end platform can only be useful for knocking out the maximum “Yops” through the most multi-threaded mode with a large command queue depth. It’s just a pity that from the point of view practical work this is absolutely spherical synthetics in a vacuum :)

On the recording, the situation has not changed fundamentally - in every sense. But what’s funny is that on both systems the PCIe 2.0 x4 mode in the “processor” slot turned out to be the fastest. On both! And with multiple checks/rechecks. At this point you can’t help but think about whether you need these are your new standards Or is it better not to rush anywhere at all...

When working with blocks of different sizes, the theoretical idyll is shattered by the fact that increasing the speed of the interface still makes sense. The resulting figures are such that a couple of PCIe 2.0 lanes would be enough, but in reality in this case the performance is lower than that of PCIe 3.0 x4, albeit not by several times. And in general, here the budget platform “clogs” the top one to a much greater extent. But it is precisely this kind of operation that is found mainly in application software, i.e. this diagram is the closest to reality. As a result, it is not surprising that thick interfaces and fashionable protocols do not provide any “wow” effect. More precisely, those switching from mechanics will be given, but exactly the same as any solid-state drive with any interface will provide him.

Total

To make it easier to perceive the picture of the hospital as a whole, we used the score given by the program (total - for reading and writing), normalizing it according to the PCIe 2.0 x4 “chipset” mode: on this moment it is the one that is most widely available, since it is found even on LGA1155 or AMD platforms without the need to “offend” the video card. In addition, it is equivalent to PCIe 3.0 x2, which budget controllers are preparing to master. Yes and on the new one AMD platform AM4, again, this is the mode that can be obtained without affecting the discrete video card.

So what do we see? The use of PCIe 3.0 x4, if possible, is certainly preferable, but not necessary: ​​it brings literally 10% additional performance to mid-class NVMe drives (in its initially top segment). And even then - due to operations that, in general, are not so often encountered in practice. Why is this particular option implemented in this case? Firstly, there was such an opportunity, but the reserve is not enough for the pocket. Secondly, there are drives even faster than our test Patriot Hellfire. Thirdly, there are areas of activity where loads that are “atypical” for a desktop system are quite typical. Moreover, this is where the performance of the data storage system, or at least the ability to make part of it very fast, is most critical. But to the usual personal computers this is all irrelevant.

In them, as we see, the use of PCIe 2.0 x2 (or, accordingly, PCIe 3.0 x1) does not lead to a dramatic decrease in performance - only by 15-20%. And this despite the fact that in this case we limited the potential capabilities of the controller by four times! For many operations this throughput is sufficient. One PCIe 2.0 line is no longer enough, so it makes sense for controllers to support PCIe 3.0 - and in conditions of severe shortage of lines in modern system this will work quite well. In addition, x4 width is useful - even if there is no support for modern versions of PCIe in the system, it will still allow you to work at normal speed (albeit slower than it could potentially) if there is a more or less wide slot.

In principle, a large number of scenarios in which the flash memory itself turns out to be the bottleneck (yes, this is possible and is inherent not only in mechanics) leads to the fact that the four lanes of the third version of PCIe on this drive are about 3.5 times faster than the first one - the theoretical throughput of these two cases differs by 16 times. Which, of course, does not mean that you need to rush to master very slow interfaces - their time is gone forever. It’s just that many of the possibilities of fast interfaces can only be realized in the future. Or under conditions that the average user regular computer will never directly encounter in life (with the exception of those who like to measure themselves with who knows what). Actually, that's all.

The PCI Express standard is one of the foundations modern computers. PCI Express slots have long occupied a strong place on any desktop computer motherboard, displacing other standards, such as PCI. But even the PCI Express standard has its own variations and connection patterns that differ from each other. On new motherboards, starting around 2010, you can see a whole scattering of ports on one motherboard, designated as PCIE or PCI-E, which may differ in the number of lines: one x1 or several x2, x4, x8, x12, x16 and x32.

So, let's find out why there is such confusion among the seemingly simple PCI Express peripheral port. And what is the purpose of each PCI Express x2, x4, x8, x12, x16 and x32 standard?

What is the PCI Express bus?

Back in the 2000s, when the transition took place from the aging PCI standard (extension - interconnection of peripheral components) to PCI Express, the latter had one huge advantage: instead of a serial bus, which was PCI, a point-to-point access bus was used. This meant that each individual PCI port and the cards installed in it could take full advantage of the maximum bandwidth without interfering with each other, as happened with a PCI connection. In those days the quantity peripheral devices There were plenty of cards inserted into expansion cards. Network cards, audio cards, TV tuners, and so on - all required a sufficient amount of PC resources. But unlike the PCI standard, which used a common bus for data transfer with multiple devices connected in parallel, PCI Express, when considered in general, is a packet network with a star topology.

PCI Express x16, PCI Express x1 and PCI on one board

In layman's terms, imagine your desktop PC as a small store with one or two salespeople. The old PCI standard was like a grocery store: everyone waited in the same line to be served, experiencing speed issues with the limitation of one salesperson behind the counter. PCI-E is more like a hypermarket: each customer follows his own individual route for groceries, and at the checkout, several cashiers take the order at once.

Obviously, a hypermarket is several times faster than a regular store in terms of speed of service, due to the fact that the store cannot afford the capacity of more than one salesperson with one cash register.

Also with dedicated data bandwidths for each expansion card or integrated components motherboard.

The influence of the number of lines on throughput

Now, to extend our store and hypermarket metaphor, imagine that each department of the hypermarket has its own cashiers reserved just for them. This is where the idea of ​​multiple data lanes comes into play.

PCI-E has gone through many changes since its inception. These days, new motherboards typically use version 3 of the standard, with the faster version 4 becoming more common, with version 5 expected in 2019. But different versions use the same physical connections, and these connections can be made in four main sizes: x1, x4, x8 and x16. (x32 ports exist, but are extremely rare on regular computer motherboards).

The different physical sizes of PCI-Express ports make it possible to clearly separate them by the number of simultaneous connections with motherboard: The larger the port physically, the more maximum connections it is capable of transmitting to or from the card. These connections are also called lines. One line can be thought of as a track consisting of two signal pairs: one for sending data and the other for receiving.

Different versions of the PCI-E standard allow you to use different speeds on every lane. But generally speaking, the more lanes there are on a single PCI-E port, the faster data can flow between the peripheral and the rest of the computer.

Returning to our metaphor: if we are talking about one seller in a store, then the x1 strip will be this only seller serving one client. A store with 4 cashiers already has 4 lines x4. And so on, you can assign cashiers by the number of lines, multiplying by 2.

Various PCI Express cards

Types of devices using PCI Express x2, x4, x8, x12, x16 and x32

For the PCI Express 3.0 version, the overall maximum data transfer speed is 8 GT/s. In reality, the speed for the PCI-E 3 version is slightly less than one gigabyte per second per lane.

Thus, a device using a PCI-E x1 port, for example, is low-power sound card or Wi-Fi antenna will be able to transmit data at a maximum speed of 1 Gbit/s.

A card that physically fits into a larger slot - x4 or x8, for example, a USB 3.0 expansion card will be able to transfer data four or eight times faster, respectively.

The transfer speed of PCI-E x16 ports is theoretically limited to a maximum bandwidth of about 15 Gbps. This is more than enough in 2017 for all modern graphics cards developed by NVIDIA and AMD.

Majority discrete video cards use PCI-E x16 slot

The PCI Express 4.0 protocol allows the use of 16 GT/s, and PCI Express 5.0 will use 32 GT/s.

But currently there are no components that could use this number of lanes with maximum throughput. Modern high-end graphics cards usually use x16 PCI Express 3.0. It makes no sense to use the same lanes for a network card that will only use one lane on the x16 port, since the Ethernet port is only capable of transferring data up to one gigabit per second (which is about one-eighth the throughput of one PCI-E lane - remember: eight bits in one byte).

There are PCI-E SSDs on the market that support the x4 port, but they look set to be replaced by the rapidly evolving new M.2 standard. For solid state drives, which can also use the PCI-E bus. High quality network cards and enthusiast hardware such as RAID controllers use a combination of x4 and x8 formats.

PCI-E port and lane sizes may vary

This is one of the most confusing problems with PCI-E: a port can be made in the x16 form factor, but not have enough lanes to carry data through, for example, just x4. This is because even though PCI-E can carry an unlimited number of individual connections, there is still a practical limit to the chipset's bandwidth capacity. Cheaper motherboards with lower-end chipsets may only have one x8 slot, even if that slot can physically accommodate an x16 form factor card.

Additionally, motherboards aimed at gamers include up to four full PCI-E slots with x16 and the same number of lanes for maximum bandwidth.

Obviously this can cause problems. If the motherboard has two x16 slots, but one of them only has x4 lanes, then adding a new graphics card will reduce the performance of the first by as much as 75%. This is, of course, only a theoretical result. The architecture of motherboards is such that you will not see a sharp drop in performance.

The correct configuration of two graphics video cards should use exactly two x16 slots if you want maximum comfort from a tandem of two video cards. The manual at the office will help you find out how many lines a particular slot has on your motherboard. manufacturer's website.

Sometimes manufacturers even mark the number of lines on the motherboard PCB next to the slot

You need to know that a shorter x1 or x4 card can physically fit into a longer x8 or x16 slot. The pin configuration of the electrical contacts makes this possible. Naturally, if the card is physically larger than the slot, then you won’t be able to insert it.

Therefore, remember, when purchasing expansion cards or upgrading current ones, you must always remember both the size of the PCI Express slot and the number of lanes required.

Spring 1991 Intel company completes development of the first prototype version of the PCI bus. The engineers were tasked with developing an inexpensive and high-performance solution that would realize the capabilities of the 486, Pentium and Pentium Pro processors. In addition, it was necessary to take into account the mistakes made by VESA when designing the VLB bus (the electrical load did not allow connecting more than 3 expansion cards), and also to implement automatic setup devices.

In 1992, the first version of the PCI bus appeared, Intel announced that the bus standard would be open, and created the PCI Special Interest Group. Thanks to this, any interested developer has the opportunity to create devices for the PCI bus without having to purchase a license. The first version of the bus had a clock frequency of 33 MHz, could be 32- or 64-bit, and devices could operate with signals of 5 V or 3.3 V. Theoretically, the bus throughput was 133 MB / s, but in reality the throughput was about 80 MB/s

Main characteristics:

• bus frequency - 33.33 or 66.66 MHz, synchronous transmission;
• bus width - 32 or 64 bits, multiplexed bus (address and data are transmitted over the same lines);
• peak throughput for the 32-bit version operating at 33.33 MHz is 133 MB/s;
• memory address space - 32 bits (4 bytes);
• address space of I/O ports - 32 bits (4 bytes);
• configuration address space (for one function) - 256 bytes;
• voltage - 3.3 or 5 V.

Photos of connectors:

MiniPCI - 124 pin
MiniPCI Express MiniSata/mSATA - 52 pin
Apple MBA SSD, 2012
Apple SSD, 2012
Apple PCIe SSD
MXM, Graphics Card, 230 / 232 pin
MXM2 NGIFF 75 pins KEY A PCIe x2 KEY B PCIe x4 Sata SMBus
MXM3, Graphics Card, 314 pin
PCI 5V
PCI Universal
PCI-X 5v
AGP Universal
AGP 3.3v
AGP 3.3 v + ADS Power
PCIe x1
PCIe x16
Custom PCIe
ISA 8bit
ISA 16bit
eISA
VESA
NuBus
PDS
PDS
Apple II/GS Expasion slot
PC/XT/AT expasion bus 8 bit
ISA (industry standard architecture) - 16 bit
eISA
MBA - Micro Bus architecture 16 bit
MBA - Micro Bus architecture with 16 bit video
MBA - Micro Bus architecture 32 bit
MBA - Micro Bus architecture with 32 bit video
ISA 16 + VLB (VESA)
Processor Direct Slot PDS
601 Processor Direct Slot PDS
LC Processor Direct Slot PERCH
NuBus
PCI (Peripheral Computer Interconnect) - 5v
PCI 3.3v
CNR (Communications / network riser)
AMR (Audio/Modem Riser)
ACR (Advanced communication riser)
PCI-X (Peripheral PCI) 3.3v
PCI-X 5v
PCI 5v + RAID option - ARO
AGP 3.3v
AGP 1.5v
AGP Universal
AGP Pro 1.5v
AGP Pro 1.5v+ADC power
PCIe (peripheral component interconnect express) x1
PCIe x4
PCIe x8
PCIe x16

PCI 2.0

The first version of the basic standard to become widespread used both cards and slots with a signal voltage of only 5 volts. Peak throughput - 133 MB/s.

PCI 2.1 - 3.0

They differed from version 2.0 in the possibility of simultaneous operation of several bus masters (English bus-master, so-called competitive mode), as well as the appearance of universal expansion cards capable of operating both in slots using a voltage of 5 volts, and in slots using 3 .3 volts (with a frequency of 33 and 66 MHz, respectively). Peak throughput for 33 MHz is 133 MB/s, and for 66 MHz it is 266 MB/s.

• Version 2.1 - work with cards designed for a voltage of 3.3 volts, and the presence of appropriate power lines were optional.
• Version 2.2 - expansion cards made in accordance with these standards have a universal power connector key and are able to work in many later types of PCI bus slots, as well as, in some cases, in version 2.1 slots.
• Version 2.3 - Incompatible with PCI cards designed to use 5 volts, despite the continued use of 32-bit slots with a 5 volt key. Expansion cards have a universal connector, but are not able to work in 5-volt slots of earlier versions (up to 2.1 inclusive).
• Version 3.0 - completes the transition to 3.3 volt PCI cards, 5 volt PCI cards are no longer supported.

PCI 64

An extension of the basic PCI standard, introduced in version 2.1, that doubles the number of data lanes, and therefore the throughput. The PCI 64 slot is an extended version of the regular PCI slot. Formally, the compatibility of 32-bit cards with 64-bit slots (provided there is a common supported signal voltage) is full, but the compatibility of a 64-bit card with 32-bit slots is limited (in any case there will be a loss of performance). Operates at a clock frequency of 33 MHz. Peak throughput - 266 MB/s.

• Version 1 - uses a 64-bit PCI slot and a voltage of 5 volts.
• Version 2 - uses a 64-bit PCI slot and a voltage of 3.3 volts.

PCI 66

PCI 66 is a 66 MHz evolution of PCI 64; uses 3.3 volts in the slot; the cards have a universal or 3.3 V form factor. Peak throughput is 533 MB/s.

PCI 64/66

The combination of PCI 64 and PCI 66 allows for four times the data transfer speed of the basic PCI standard; uses 64-bit 3.3V slots, compatible only with universal ones, and 3.3V 32-bit expansion cards. PCI64/66 standard cards have either a universal (but with limited compatibility with 32-bit slots) or a 3.3-volt form factor (the latter option is fundamentally incompatible with 32-bit 33-MHz slots of popular standards). Peak throughput - 533 MB/s.

PCI-X

PCI-X 1.0 is an expansion of the PCI64 bus with the addition of two new operating frequencies, 100 and 133 MHz, as well as a separate transaction mechanism to improve performance when multiple devices operate simultaneously. Generally backward compatible with all 3.3V and generic PCI cards. PCI-X cards are typically implemented in 64-bit 3.3B format and have limited backward compatibility with PCI64/66 slots, and some PCI-X cards are universal format and are capable of working (although this has almost no practical value) in regular PCI 2.2/2.3. In difficult cases, in order to be completely confident in the functionality of the combination of the motherboard and expansion card, you need to look at the compatibility lists of the manufacturers of both devices.

PCI-X 2.0

PCI-X 2.0 - further expansion of the capabilities of PCI-X 1.0; frequencies of 266 and 533 MHz have been added, as well as parity error correction during data transmission (ECC). Allows splitting into 4 independent 16-bit buses, which is used exclusively in built-in and industrial systems ; signal voltage reduced to 1.5 V, but retained backward compatibility connectors with all cards using a signal voltage of 3.3 V. Currently, for the non-professional segment of the high-performance computer market (powerful workstations and entry-level servers), in which it is used PCI-X bus, very few motherboards with bus support are produced. An example of a motherboard for this segment is ASUS P5K WS. In the professional segment it is used in RAID controllers and SSD drives for PCI-E.

Mini PCI

Form factor PCI 2.2, intended for use mainly in laptops.

PCI Express

PCI Express, or PCIe, or PCI-E (also known as 3GIO for 3rd Generation I/O; not to be confused with PCI-X and PXI) - computer bus(although at the physical level it is not a bus, being a point-to-point connection), using software model PCI buses and a high-performance physical protocol based on serial data transmission. The development of the PCI Express standard was started by Intel after abandoning the InfiniBand bus. Officially, the first basic PCI Express specification appeared in July 2002. The development of the PCI Express standard is carried out by the PCI Special Interest Group.

Unlike the PCI standard, which used a common bus for data transfer with multiple devices connected in parallel, PCI Express, in general, is a packet network with star topology. PCI Express devices communicate with each other through a medium formed by switches, with each device directly connected by a point-to-point connection to the switch. In addition, the PCI Express bus supports:

• hot swap cards;
• guaranteed bandwidth (QoS);
• energy management;
• monitoring the integrity of transmitted data.

The PCI Express bus is intended to be used only as a local bus. Since the PCI Express software model is largely inherited from PCI, existing systems and controllers can be modified to use the PCI Express bus by replacing only physical level, without modification software. The high peak performance of the PCI Express bus allows it to be used instead of AGP buses, and even more so PCI and PCI-X. De facto, PCI Express replaced these buses in personal computers.

• MiniCard (Mini PCIe) - replacement for the Mini PCI form factor. The Mini Card connector has the following buses: x1 PCIe, 2.0 and SMBus.
  • M.2 is the second version of Mini PCIe, up to x4 PCIe and SATA.
• ExpressCard - similar to PCMCIA form factor. The ExpressCard connector supports x1 PCIe and USB 2.0 buses; ExpressCard cards support hot plugging.
• AdvancedTCA, MicroTCA - form factor for modular telecommunications equipment.
  
• Mobile PCI Express Module (MXM) is an industrial form factor created for laptops by NVIDIA. It is used to connect graphics accelerators.
• PCI Express cable specifications allow the length of one connection to reach tens of meters, which makes it possible to create a computer whose peripheral devices are located at a considerable distance.
  
• StackPC - specification for building stackable computer systems. This specification describes the expansion connectors StackPC, FPE and their relative positions.

Despite the fact that the standard allows x32 lines per port, such solutions are physically quite bulky and are not available.

Year release	Version PCI Express	Coding	Speed transfers	Bandwidth on x lines
				×1	×2	×4	×8	×16
2002	1.0	8b/10b	2.5 GT/s	2	4	8	16	32
2007	2.0	8b/10b	5 GT/s	4	8	16	32	64
2010	3.0	128b/130b	8 GT/s	~7,877	~15,754	~31,508	~63,015	~126,031
2017	4.0	128b/130b	16 GT/s	~15,754	~31,508	~63,015	~126,031	~252,062
2019	5.0	128b/130b	32 GT/s	~32	~64	~128	~256	~512

PCI Express 2.0

The PCI-SIG released the PCI Express 2.0 specification on January 15, 2007. Key innovations in PCI Express 2.0:

• Increased throughput: bandwidth of one line 500 MB/s, or 5 GT/s ( Gigatransactions/s).
• Improvements have been made to the transfer protocol between devices and the software model.
• Dynamic speed control (to control the communication speed).
• Bandwidth Alert (to notify software of changes in bus speed and width).
• Access Control Services - Optional point-to-point transaction management capabilities.
• Execution timeout control.
• Function level reset is an optional mechanism for resetting PCI functions within a PCI device.
• Redefining the power limit (to redefine the slot power limit when connecting devices that consume more power).

PCI Express 2.0 is fully compatible with PCI Express 1.1 (old ones will work in motherboards with new connectors, but only at a speed of 2.5 GT/s, since old chipsets cannot support double data transfer rates; new video adapters will work without problems in old PCI Express 1.x connectors).

PCI Express 2.1

In terms of physical characteristics (speed, connector) it corresponds to 2.0; in the software part, functions have been added that are planned to be fully implemented in version 3.0. Since most motherboards are sold with version 2.0, having only a video card with 2.1 does not allow you to use 2.1 mode.

PCI Express 3.0

In November 2010, the specifications for PCI Express 3.0 were approved. The interface has a data transfer rate of 8 GT/s ( Gigatransactions/s). But despite this, its actual throughput was still doubled compared to the PCI Express 2.0 standard. This was achieved thanks to a more aggressive 128b/130b encoding scheme, where 128 bits of data sent over the bus are encoded in 130 bits. At the same time, full compatibility with previous versions PCI Express. PCI Express 1.x and 2.x cards will work in slot 3.0 and, conversely, a PCI Express 3.0 card will work in slots 1.x and 2.x.

PCI Express 4.0

The PCI Special Interest Group (PCI SIG) stated that PCI Express 4.0 could be standardized before the end of 2016, but in mid-2016, when a number of chips were already being prepared for production, media reported that standardization was expected in early 2017. will have a throughput of 16 GT/s, that is, it will be twice as fast as PCIe 3.0.

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PCI - Express (PCIePCI -E)– serial, universal bus first unveiled July 22, 2002 of the year.

Is general, unifying bus for all nodes motherboard, in which all devices connected to it coexist. Came to replace an outdated tire PCI and its variations AGP, due to increased requirements for bus throughput and the inability to improve the speed performance of the latter at reasonable cost.

The tire acts as switch, simply sending a signal from one point to another without changing it. This allows, without obvious loss of speed, with minimal changes and errors transmit and receive a signal.

Data on the bus goes simplex(full duplex), that is, simultaneously in both directions at the same speed, and signal along the lines flows continuously, even when the device is turned off (as D.C., or a bit signal of zeros).

Synchronization constructed using a redundant method. That is, instead of 8 bit information is transmitted 10 bits, two of which are official (20% ) and serve in a certain sequence beacons For synchronization clock generators or identifying errors. Therefore, the declared speed for one line in 2.5 Gbps, is actually equal to approximately 2.0 Gbps real.

Nutrition each device on the bus, selected separately and regulated using technology ASPM (Active State Power Management). It allows when the device is idle (without sending a signal) lower its clock generator and put the bus into mode reduced energy consumption . If no signal is received within a few microseconds, the device considered inactive and switches to mode expectations(time depends on device type).

Speed ​​characteristics in two directions PCI - Express 1.0 :*

1 x PCI-E~ 500 Mbps

4x PCI-E~ 2 Gbps

8 x PCI-E~ 4 Gbps

16x PCI-E~ 8 Gbps

32x PCI-E~ 16 Gbps

*Data transfer speed in one direction is 2 times lower than these indicators

January 15, 2007, PCI-SIG released an updated specification called PCI-Express 2.0

The main improvement was in 2 times increased speed data transmission ( 5.0 GHz, against 2.5GHz V old version). Also improved point-to-point communication protocol(dot-to-dot), modified software component and added system software monitoring according to the tire speed. At the same time, it was preserved compatibility with protocol versions PCI-E 1.x

IN new version standard ( PCI -Express 3.0 ), the main innovation will be modified coding system And synchronization. Instead of 10 bit systems ( 8 bit information, 2 bits official), will apply 130 bit (128 bit information, 2 bits official). This will reduce losses in speed from 20% to ~1.5%. Will also be redesigned synchronization algorithm transmitter and receiver, improved PLL(phase-locked loop).Transmission speed expected to increase 2 times(compared to PCI-E 2.0), wherein compatibility will remain with previous versions PCI-Express.

PCI Express was born on July 22, 2002. Its creator was Intel Corporation, it was on this day that it became available. technical documentation. Until this point, at the development stage, the “bus” had the designation 3GIO (third generation input-output). These two names were branded by PCI SIG (the organization that now promotes this standard).

PCIe is a high-performance point-to-point connection that replaced the PCI bus (read as PiSiI). Physically different in that does not use common dedicated lines for communication with the processor, but has its own for each connected device. Signal transmission voltage is 0.8 volts. Each channel represents two physical conductors (four contacts). When transmitting information, eight bits are encoded as ten, which provides good protection against interference.

Its common software model is similar to its predecessor. For data transmission, which in this case is carried out sequentially, a physical protocol with high bandwidth is used. Used to connect high-performance peripheral devices. The pseudobus has been assigned the role of a local data exchange channel.

Differences between PCI Express and PCI

PCI is primarily a bus, that is, a common channel that is shared by all devices connected to it. And PCI Express - for each device has its own paths, which are physically designed. Continuity of the digital structure of information transfer simplifies adaptation existing products previously produced to work with the old tire. In production, it turns out that it is enough to make minor amendments to the design and you can produce the same variety, but with a new interface.

Operating principle, compatibility

Being two-way, the connection transmits data serially in batch mode. Throughput depends on the implementation in each specific case. PCI Express can be one (1x), two or more transport lines (2X, 4X, 6x, 8x, 12x, 16x, 32x), which determines the length of the slot on the motherboard. It is typical that the equipment is capable of working with any of them, but expansion cards adapted for serious speeds cannot physically fit into less productive slots, simply not matching in size. Although, on the contrary, less productive expansion boards that have short contact groups easily fit into larger ones and work correctly.

In the table we have provided a summary table of the ratio number of lines and bandwidth:

Available now several specifications tires:

• PCI Express 1.0 and 1.1. The first and least productive solutions, which are now practically not used. They are stored on old boards that are still in use.
• 2.0. All performance-determining qualities have been reworked and improved, logical protocols have been improved, communication management has been comprehensively optimized, and auto-detection of plug-in modules has been improved.
• External cable specificationPCIe. Allows you to connect equipment with a cable up to 10 m long.
• 2.1. An intermediate analogue of 2.0 with some advanced features preceding the appearance of 3.0.
• 3.0. Speeds of 8 gigatransactions per second (GT/s) made possible thanks to new system encryption 128b/130b. Thus, the difference between pci 2.0 and 3.0 is in encryption and data transfer speed.
• 4.0. The standard was recently approved - October 5, 2017. Compared to the previous one, the speed is doubled. Individual indicators related to virtualization have increased, and the transmission of data packets has been optimized.
• 5.0. The release is tentatively planned for winter-spring 2019. Expanded support for applications that visualize virtual reality is announced.

Existing connectors and types of ports

There are many connection ports for the interface. Let's look at some of the most common ones:

• MiniPCI-E (M.2). Common bus for some of the most common computer protocols and devices with x1 and x4 PCIe interface.
• ExpressCard. A similar connector, but with a bus output only for x1 PCIe.
• AdvancedTCA, MicroTCA – ports for communication equipment.
• MobilePCIExpressModule (MXM) – developed by NVIDIA for connecting video cards.
• StackPC – for creating supercomputers, allows you to scale computing devices.

How to find out the PCI Express version on your motherboard

It is usually written near the slot itself on the motherboard, but can be written elsewhere. Still often write on the packaging motherboard and indicated in the manual. You can go to the official website and enter the serial number of the motherboard into the search, or try to search for the specification by name and revision (variety).

The most common peripherals for the most productive x16 slots are video cards and SSD drives. Controllers such as additional USB, SATA and similar high-speed ports or various adapters, such as sound, music cards, Wi-Fi modules, are also not uncommon.

Video card

HDD

Wireless adapter

PCI Express pinout

It is easier to comprehensively show the location of communication line outputs using the example of the lines of the largest and fastest port.

PCI-Express 16x slot contact group device:

The PCIe connection has proven its effectiveness. It meets all modern requirements for information transfer speed and operational stability. Possessing huge potential modernization allows you to maintain the compatibility of numerous devices of different generations: controllers, adapters. In addition, it serves as a broad channel for increasing computing power. A special and unexpected place for the application of this technology is the telecommunications sector.

Introduced in 2002, this type of transport data is still the most relevant, widespread, continuously developing and still promising.